12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302SN/A */ 312SN/A 3211793Sbrandon.potter@amd.com#include "cpu/pc_event.hh" 3311793Sbrandon.potter@amd.com 342SN/A#include <algorithm> 352SN/A#include <string> 362SN/A#include <utility> 372SN/A 385882Snate@binkert.org#include "base/debug.hh" 391492SN/A#include "base/trace.hh" 401717SN/A#include "cpu/base.hh" 412680Sktlim@umich.edu#include "cpu/thread_context.hh" 428232Snate@binkert.org#include "debug/PCEvent.hh" 434167Sbinkertn@umich.edu#include "sim/core.hh" 442190SN/A#include "sim/system.hh" 452SN/A 462SN/Ausing namespace std; 472SN/A 482SN/APCEventQueue::PCEventQueue() 492SN/A{} 502SN/A 512SN/APCEventQueue::~PCEventQueue() 522SN/A{} 532SN/A 542SN/Abool 552SN/APCEventQueue::remove(PCEvent *event) 562SN/A{ 572SN/A int removed = 0; 582SN/A range_t range = equal_range(event); 598991SAli.Saidi@ARM.com iterator i = range.first; 608991SAli.Saidi@ARM.com while (i != range.second && 618991SAli.Saidi@ARM.com i != pc_map.end()) { 622SN/A if (*i == event) { 632SN/A DPRINTF(PCEvent, "PC based event removed at %#x: %s\n", 642SN/A event->pc(), event->descr()); 658991SAli.Saidi@ARM.com i = pc_map.erase(i); 662SN/A ++removed; 678991SAli.Saidi@ARM.com } else { 688991SAli.Saidi@ARM.com i++; 692SN/A } 708991SAli.Saidi@ARM.com 712SN/A } 722SN/A 732SN/A return removed > 0; 742SN/A} 752SN/A 762SN/Abool 772SN/APCEventQueue::schedule(PCEvent *event) 782SN/A{ 792SN/A pc_map.push_back(event); 802SN/A sort(pc_map.begin(), pc_map.end(), MapCompare()); 812SN/A 822SN/A DPRINTF(PCEvent, "PC based event scheduled for %#x: %s\n", 832SN/A event->pc(), event->descr()); 842SN/A 852SN/A return true; 862SN/A} 872SN/A 882SN/Abool 892680Sktlim@umich.eduPCEventQueue::doService(ThreadContext *tc) 902SN/A{ 918670Ss052838@student.dtu.dk // This will fail to break on Alpha PALcode addresses, but that is 928670Ss052838@student.dtu.dk // a rare use case. 938670Ss052838@student.dtu.dk Addr pc = tc->instAddr(); 942SN/A int serviced = 0; 952SN/A range_t range = equal_range(pc); 962SN/A for (iterator i = range.first; i != range.second; ++i) { 972SN/A // Make sure that the pc wasn't changed as the side effect of 982SN/A // another event. This for example, prevents two invocations 992SN/A // of the SkipFuncEvent. Maybe we should have separate PC 1002SN/A // event queues for each processor? 1018670Ss052838@student.dtu.dk if (pc != tc->instAddr()) 1022SN/A continue; 1032SN/A 1042SN/A DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n", 1052SN/A (*i)->pc(), (*i)->descr()); 1062SN/A 1072680Sktlim@umich.edu (*i)->process(tc); 1082SN/A ++serviced; 1092SN/A } 1102SN/A 1112SN/A return serviced > 0; 1122SN/A} 1132SN/A 1142SN/Avoid 1152SN/APCEventQueue::dump() const 1162SN/A{ 1172SN/A const_iterator i = pc_map.begin(); 1182SN/A const_iterator e = pc_map.end(); 1192SN/A 1202SN/A for (; i != e; ++i) 1217823Ssteve.reinhardt@amd.com cprintf("%d: event at %#x: %s\n", curTick(), (*i)->pc(), 1222SN/A (*i)->descr()); 1232SN/A} 1242SN/A 1252SN/APCEventQueue::range_t 1262SN/APCEventQueue::equal_range(Addr pc) 1272SN/A{ 1282SN/A return std::equal_range(pc_map.begin(), pc_map.end(), pc, MapCompare()); 1292SN/A} 1302SN/A 1311885SN/ABreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr, 1321885SN/A bool del) 1331885SN/A : PCEvent(q, desc, addr), remove(del) 1342SN/A{ 1352SN/A} 1362SN/A 1372SN/Avoid 1382680Sktlim@umich.eduBreakPCEvent::process(ThreadContext *tc) 1392SN/A{ 1402680Sktlim@umich.edu StringWrap name(tc->getCpuPtr()->name() + ".break_event"); 1411646SN/A DPRINTFN("break event %s triggered\n", descr()); 1428231Snate@binkert.org Debug::breakpoint(); 1432SN/A if (remove) 1442SN/A delete this; 1452SN/A} 1462SN/A 1472SN/Avoid 1482130SN/Asched_break_pc_sys(System *sys, Addr addr) 1492SN/A{ 1501885SN/A new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true); 1512SN/A} 1522SN/A 1532SN/Avoid 1542130SN/Asched_break_pc(Addr addr) 1552SN/A{ 1562SN/A for (vector<System *>::iterator sysi = System::systemList.begin(); 1572SN/A sysi != System::systemList.end(); ++sysi) { 1582SN/A sched_break_pc_sys(*sysi, addr); 1592SN/A } 1602SN/A 1612SN/A} 1629649SAndreas.Sandberg@ARM.com 1639649SAndreas.Sandberg@ARM.comPanicPCEvent::PanicPCEvent(PCEventQueue *q, const std::string &desc, Addr pc) 1649649SAndreas.Sandberg@ARM.com : PCEvent(q, desc, pc) 1659649SAndreas.Sandberg@ARM.com{ 1669649SAndreas.Sandberg@ARM.com} 1679649SAndreas.Sandberg@ARM.com 1689649SAndreas.Sandberg@ARM.comvoid 1699649SAndreas.Sandberg@ARM.comPanicPCEvent::process(ThreadContext *tc) 1709649SAndreas.Sandberg@ARM.com{ 1719649SAndreas.Sandberg@ARM.com StringWrap name(tc->getCpuPtr()->name() + ".panic_event"); 1729649SAndreas.Sandberg@ARM.com panic(descr()); 1739649SAndreas.Sandberg@ARM.com} 174