16899SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 26899SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36899SN/A# All rights reserved. 46899SN/A# 56899SN/A# Redistribution and use in source and binary forms, with or without 66899SN/A# modification, are permitted provided that the following conditions are 76899SN/A# met: redistributions of source code must retain the above copyright 86899SN/A# notice, this list of conditions and the following disclaimer; 96899SN/A# redistributions in binary form must reproduce the above copyright 106899SN/A# notice, this list of conditions and the following disclaimer in the 116899SN/A# documentation and/or other materials provided with the distribution; 126899SN/A# neither the name of the copyright holders nor the names of its 136899SN/A# contributors may be used to endorse or promote products derived from 146899SN/A# this software without specific prior written permission. 156899SN/A# 166899SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176899SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186899SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196899SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206899SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216899SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226899SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236899SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246899SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256899SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266899SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276899SN/A# 286899SN/Afrom m5.params import * 296899SN/Afrom m5.proxy import * 306899SN/A 3113892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 3213665Sandreas.sandberg@arm.com 3313892Sgabeblack@google.comclass RubyTester(ClockedObject): 346899SN/A type = 'RubyTester' 359338SAndreas.Sandberg@arm.com cxx_header = "cpu/testers/rubytest/RubyTester.hh" 368932SBrad.Beckmann@amd.com num_cpus = Param.Int("number of cpus / RubyPorts") 3711266SBrad.Beckmann@amd.com cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches") 3811266SBrad.Beckmann@amd.com cpuInstPort = VectorMasterPort("cpu ports to only inst caches") 3911266SBrad.Beckmann@amd.com cpuDataPort = VectorMasterPort("cpu ports to only data caches") 406899SN/A checks_to_complete = Param.Int(100, "checks to complete") 416899SN/A deadlock_threshold = Param.Int(50000, "how often to check for deadlock") 426899SN/A wakeup_frequency = Param.Int(10, "number of cycles between wakeups") 438184Ssomayeh@cs.wisc.edu check_flush = Param.Bool(False, "check cache flushing") 448832SAli.Saidi@ARM.com system = Param.System(Parent.any, "System we belong to") 45