Searched hist:53 (Results 251 - 275 of 402) sorted by relevance
/gem5/src/sim/ | ||
H A D | root.cc | 7826:c06505ff551e Mon Jan 10 07:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Root: Get rid of unnecessary includes in root.cc. |
H A D | byteswap.hh | 12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | init.cc | 7502:3ef7ff12c788 Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: Add mechanism to override code compiled into the exectuable If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature! |
/gem5/src/arch/x86/ | ||
H A D | faults.cc | 6048:65a321a3a691 Sun Apr 19 05:53:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INIT IPI. |
/gem5/src/arch/mips/ | ||
H A D | isa_traits.hh | 6974:4d4903a3e7c5 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> O3PCU: Split loads and stores that cross cache line boundaries. When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. |
/gem5/src/arch/alpha/ | ||
H A D | isa_traits.hh | 6974:4d4903a3e7c5 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> O3PCU: Split loads and stores that cross cache line boundaries. When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. |
/gem5/src/mem/cache/tags/ | ||
H A D | base_set_assoc.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/configs/example/ | ||
H A D | ruby_mem_test.py | 7938:685719afafe6 Tue Feb 08 18:53:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> memtest: due to contention increase, increased deadlock threshold |
/gem5/src/arch/arm/insts/ | ||
H A D | pred_inst.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | ldr.isa | 7187:53d0ec9111bc Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make ldrs into the PC and ldm exception return do interworking branches. |
/gem5/src/arch/power/isa/ | ||
H A D | decoder.isa | 12692:1eaaa1d75080 Fri May 04 01:53:00 EDT 2018 Matt Sinclair <mattdsinclair@gmail.com> arch-x86, arch-power: fix calls to bits and insertBits The bits and insertBits assume the first bit is the larger bit and the last bit is the smaller bit. This commit fixes several X86 and Power calls to these functions that incorrectly assumed that first was the smaller bit. Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01 Reviewed-on: https://gem5-review.googlesource.com/10241 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/tests/configs/ | ||
H A D | rubytest-ruby.py | 9577:91cac7c9c636 Wed Mar 06 22:53:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. |
H A D | simple-timing-ruby.py | 9577:91cac7c9c636 Wed Mar 06 22:53:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. |
H A D | simple-timing-mp-ruby.py | 13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3 Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/util/ | ||
H A D | style.py | 7807:15553b536bd6 Thu Dec 30 00:53:00 EST 2010 Nathan Binkert <nate@binkert.org> style: make style hook work with pre-qrefresh and update to use new code clean up the code a little bit while we're at it. I recommend that everyone adds the pre-qrefresh hook below since it will make qref run the style hook and not just commit/qpush [extensions] style = <m5 path>/util/style.py [hooks] pretxncommit.style = python:style.check_whitespace pre-qrefresh.style = python:style.check_whitespace |
/gem5/configs/common/ | ||
H A D | MemConfig.py | 9709:fe54045c8670 Thu May 30 00:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add a LPDDR3-1600 configuration This patch adds a typical (leaning towards fast) LPDDR3 configuration based on publically available data. As expected, it looks very similar to the LPDDR2-S4 configuration, only with a slightly lower burst time. |
H A D | CacheConfig.py | 8724:7b4d80b26e35 Thu Jan 26 14:53:00 EST 2012 Ronald Dreslinski <rdreslin@umich.edu> configs: A more realistic configuration of an ARM-like processor |
/gem5/src/arch/arm/ | ||
H A D | SConscript | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/sparc/solaris/ | ||
H A D | process.cc | 13988:d579f9c76531 Fri May 03 01:53:00 EDT 2019 Gabe Black <gabeblack@google.com> sparc: Add an object file loader for linux and solaris. Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/arch/sparc/linux/ | ||
H A D | process.cc | 13988:d579f9c76531 Fri May 03 01:53:00 EDT 2019 Gabe Black <gabeblack@google.com> sparc: Add an object file loader for linux and solaris. Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/base/ | ||
H A D | bitfield.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
/gem5/src/cpu/o3/ | ||
H A D | rename_map.cc | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
/gem5/src/mem/ | ||
H A D | DRAMCtrl.py | 10536:aa97958ce2aa Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Clarify unit of DRAM controller buffer size |
/gem5/src/mem/ruby/system/ | ||
H A D | Sequencer.py | 9577:91cac7c9c636 Wed Mar 06 22:53:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | fp.isa | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
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