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14038:8ba13d8b7810 |
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01-May-2019 |
Matthew Poremba <matthew.poremba@amd.com> |
mem: Option to toggle DRAM low-power states
Adding an option to enable DRAM low-power states. The low power states can have a significant impact on application performance (sim_ticks) on the order of 2-3x, especially for compute-gpu apps. The options allows for it to easily be enabled/disabled to compare performance numbers. The option is disabled by default.
Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13665:9c7fe3811b88 |
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25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Don't assume SimObjects live in the global namespace
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files.
Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12969:52de9d619ce6 |
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04-Aug-2017 |
Matteo Andreozzi <Matteo.Andreozzi@arm.com> |
mem: Make DRAMCtrl a QoS-aware Memory Controller
This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no policy" as a default policy.
Change-Id: I48163da8c8208498cf0398b07094cb840272507f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11973 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12706:456304051464 |
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28-Mar-2017 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Add support for more flexible DRAM timing and topologies
This patch has 2 main aspects: 1) Add new parameter to adjust write-to-write delay 2) Enable support of more than 64 banks per controller
Changes for new parameter: Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L. This parameter can be used to set a unique delay between writes and between reads.
To incorporate this parameter in the controller, modified the DRAMCtrl class to have separate variables for read and write column delays. Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS as well as the new tCCD_L_WR parameter.
Changes to support more than 64 banks: Modified the logic selecting the next command (reorderQueue and minBankPrep functions). Replaced the unint64_t variables with a vector of uint32_t elements. There is a uint32_t element defined per ranks to allow up to 32 banks per rank. This will automatically scale with ranks without issue. Change will allow analysis of memory sub-systems beyond the current landscape.
Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10103 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12516:483fc7339fb1 |
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09-Feb-2018 |
Wendy Elsasser <wendy.elsasser@arm.com> |
Fix DDR4_2400_8x8 DRAMCTRL configuration
Change-Id: I7af361e146909acc158590354ab22732d4b2f3d5 Signed-off-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8101 Maintainer: Jason Lowe-Power <jason@lowepower.com>
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11837:17b37f38944a |
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14-Feb-2017 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both the channel and device data width.
Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width
Total channel width can be calculated by n*w
Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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11679:4aa51b4a2f24 |
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13-Oct-2016 |
Omar Naji <Omar.Naji@arm.com> |
mem: add DRAM powerdown current
Change-Id: I763cffe0c69f5ebbbf6a6eb12bec5c13d5d0161d Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
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11674:b4015b449dd3 |
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13-Oct-2016 |
Omar Naji <Omar.Naji@arm.com> |
mem: update DDR3 die revision
Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
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11673:9f3ccf96bb5a |
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13-Oct-2016 |
Omar Naji <Omar.Naji@arm.com> |
mem: add DRAM powerdown timing
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11672:55276af429ed |
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13-Oct-2016 |
Omar Naji <Omar.Naji@arm.com> |
mem: make DDR4 x16
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11186:2d1d51615e0e |
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03-Nov-2015 |
Erfan Azarkhish <erfan.azarkhish@unibo.it> |
mem: hmc: minor fixes
This patch performs two minor fixes to DRAMCtrl.py and xbar.hh in favor of the HMC patch series.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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11120:eef83ecab5bf |
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22-Sep-2015 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Add initial HBM configurations
Created the following HBM configurations: 1) HBM gen1 (x128/CH), 2Gb die, 4H stack, 1Gbps, 8 channels 2) HBM gen2 (x64/PC), 8Gb die, 4H stack, 1Gbps, 16 pseudo-channels
The configuration values are based on: - The HBM gen1 public JEDEC spec - Publically released data from MemCon presentations - Timing extrapolated from existing LPDDR configurations
Will adjust once specs become available.
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10891:d958fc5f4a00 |
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03-Jul-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Increase the default buffer sizes for the DDR4 controller
This patch increases the default read/write buffer sizes for the DDR4 controller config to values that are more suitable for the high bandwidth and high bank count.
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10864:83cec4049505 |
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07-Jun-2015 |
Matthias Jung <jungma@eit.uni-kl.de> |
mem: Add HMC Timing Parameters A single HMC-2500 x32 model based on:
[1] DRAMSpec: a high-level DRAM bank modelling tool developed at the University of Kaiserslautern. This high level tool uses RC (resistance-capacitance) and CV (capacitance-voltage) models to estimate the DRAM bank latency and power numbers.
[2] A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube (E. Azarkhish et. al) Assumed for the HMC model is a 30 nm technology node. The modelled HMC consists of a 4 Gbit part with 4 layers connected with TSVs. Each layer has 16 vaults and each vault consists of 2 banks per layer. In order to be able to use the same controller used for 2D DRAM generations for HMC, the following analogy is done: Channel (DDR) => Vault (HMC) device_size (DDR) => size of a single layer in a vault ranks per channel (DDR) => number of layers banks per rank (DDR) => banks per layer devices per rank (DDR) => devices per layer ( 1 for HMC). The parameters for which no input is available are inherited from the DDR3 configuration.
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10675:bb7cd7193edc |
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03-Feb-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Adjust DRAM channel interleaving defaults
This patch changes the DRAM channel interleaving default behaviour to be more representative. The default address mapping (RoRaBaCoCh) moves the channel bits towards the least significant bits, and uses 128 byte as the default channel interleaving granularity.
These defaults can be overridden if desired, but should serve as a sensible starting point for most use-cases.
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10561:e1a853349529 |
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02-Dec-2014 |
Omar Naji <Omar.Naji@arm.com> |
mem: Add a GDDR5 DRAM config
This patch adds a first cut GDDR5 config to accommodate the users combining gem5 and GPUSim. The config is based on a SK Hynix datasheet, and the Nvidia GTX580 specification. Someone from the GPUSim user-camp should tweak the default page-policy and static frontend and backend latencies.
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10536:aa97958ce2aa |
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14-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Clarify unit of DRAM controller buffer size
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10489:99d59caa4c8f |
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20-Oct-2014 |
Omar Naji <Omar.Naji@arm.com> |
mem: Add DRAM device size and check against config
This patch adds the size of the DRAM device to the DRAM config. It also compares the actual DRAM size (calculated using information from the config) to the size defined in the system. If these two values do not match gem5 will print a warning. In order to do correct DRAM research the size of the memory defined in the system should match the size of the DRAM in the config. The timing and current parameters found in the DRAM configs are defined for a DRAM device with a specific size and would differ for another device with a different size.
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10430:f958ccec628f |
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25-Jul-2014 |
Omar Naji <Omar.Naji@arm.com> |
mem: Add missig timing and current parameters to DRAM configs
This patch adds missing timing and current parameters to the existing DRAM configs. These missing timing and current parameters are required by DRAMPower for the DRAM power calculations. The missing values are datasheet values of the specified DRAMs, and the appropriate references are added for the variuos configs.
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10429:025a459edb87 |
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09-Oct-2014 |
Omar Naji <Omar.Naji@arm.com> |
mem: Remove DRAMSim2 DDR3 configuration
This patch prunes the DDR3 config that was initially created to match the default config of DRAMSim2. The config is not complete as it is, and to avoid having to maintain it, the easiest way forward is to simply prune it. Going forward we are adding power number etc to the other configurations.
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10394:70cfafa17653 |
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20-Sep-2014 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Add DDR4 bank group timing
Added the following parameter to the DRAMCtrl class: - bank_groups_per_rank
This defaults to 1. For the DDR4 case, the default is overridden to indicate bank group architecture, with multiple bank groups per rank.
Added the following delays to the DRAMCtrl class: - tCCD_L : CAS-to-CAS, same bank group delay - tRRD_L : RAS-to-RAS, same bank group delay
These parameters are only applied when bank group timing is enabled. Bank group timing is currently enabled only for DDR4 memories.
For all other memories, these delays will default to '0 ns'
In the DRAM controller model, applied the bank group timing to the per bank parameters actAllowedAt and colAllowedAt. The actAllowedAt will be updated based on bank group when an ACT is issued. The colAllowedAt will be updated based on bank group when a RD/WR burst is issued.
At the moment no modifications are made to the scheduling.
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10393:0fafa62b6c01 |
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20-Sep-2014 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Add memory rank-to-rank delay
Add the following delay to the DRAM controller: - tCS : Different rank bus turnaround delay
This will be applied for 1) read-to-read, 2) write-to-write, 3) write-to-read, and 4) read-to-write command sequences, where the new command accesses a different rank than the previous burst.
The delay defaults to 2*tCK for each defined memory class. Note that this does not correspond to one particular timing constraint, but is a way of modelling all the associated constraints.
The DRAM controller has some minor changes to prioritize commands to the same rank. This prioritization will only occur when the command stream is not switching from a read to write or vice versa (in the case of switching we have a gap in any case).
To prioritize commands to the same rank, the model will determine if there are any commands queued (same type) to the same rank as the previous command. This check will ensure that the 'same rank' command will be able to execute without adding bubbles to the command flow, e.g. any ACT delay requirements can be done under the hoods, allowing the burst to issue seamlessly.
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10217:baf8754fd5be |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Update DDR3 and DDR4 based on datasheets
This patch makes a more firm connection between the DDR3-1600 configuration and the corresponding datasheet, and also adds a DDR3-2133 and a DDR4-2400 configuration. At the moment there is also an ongoing effort to align the choice of datasheets to what is available in DRAMPower.
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10216:52c869140fc2 |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add DRAM cycle time
This patch extends the current timing parameters with the DRAM cycle time. This is needed as the DRAMPower tool expects timestamps in DRAM cycles. At the moment we could get away with doing this in a post-processing step as the DRAMPower execution is separate from the simulation run. However, in the long run we want the tool to be called during the simulation, and then the cycle time is needed.
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10212:acc1131e01d6 |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add tRTP to the DRAM controller
This patch adds the tRTP timing constraint, governing the minimum time between a read command and a precharge. Default values are provided for the existing DRAM types.
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10210:793e5ff26e0b |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add tWR to DRAM activate and precharge constraints
This patch adds the write recovery time to the DRAM timing constraints, and changes the current tRASDoneAt to a more generic preAllowedAt, capturing when a precharge is allowed to take place.
The part of the DRAM access code that accounts for the precharge and activate constraints is updated accordingly.
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10206:823f7fd1a82f |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Make DRAM read/write switching less conservative
This patch changes the read/write event loop to use a single event (nextReqEvent), along with a state variable, thus joining the two control flows. This change makes it easier to follow the state transitions, and control what happens when.
With the new loop we modify the overly conservative switching times such that the write-to-read switch allows bank preparation to happen in parallel with the bus turn around. Similarly, the read-to-write switch uses the introduced tRTW constraint.
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10146:27dfed4c8403 |
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23-Mar-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant).
As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future.
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