DRAMCtrl.py revision 10536:aa97958ce2aa
12381SN/A# Copyright (c) 2012-2014 ARM Limited 212341Snikos.nikoleris@arm.com# All rights reserved. 38711SN/A# 48711SN/A# The license below extends only to copyright in the software and shall 58711SN/A# not be construed as granting a license to any other intellectual 68711SN/A# property including but not limited to intellectual property relating 78711SN/A# to a hardware implementation of the functionality of the software 88711SN/A# licensed hereunder. You may use the software subject to the license 98711SN/A# terms below provided that you ensure that this notice is replicated 108711SN/A# unmodified and in its entirety in all distributions of the software, 118711SN/A# modified or unmodified, in source code or in binary form. 128711SN/A# 138711SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 142381SN/A# All rights reserved. 152381SN/A# 162381SN/A# Redistribution and use in source and binary forms, with or without 172381SN/A# modification, are permitted provided that the following conditions are 182381SN/A# met: redistributions of source code must retain the above copyright 192381SN/A# notice, this list of conditions and the following disclaimer; 202381SN/A# redistributions in binary form must reproduce the above copyright 212381SN/A# notice, this list of conditions and the following disclaimer in the 222381SN/A# documentation and/or other materials provided with the distribution; 232381SN/A# neither the name of the copyright holders nor the names of its 242381SN/A# contributors may be used to endorse or promote products derived from 252381SN/A# this software without specific prior written permission. 262381SN/A# 272381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382381SN/A# 392665SN/A# Authors: Andreas Hansson 402665SN/A# Ani Udipi 412772SN/A 428715SN/Afrom m5.params import * 438922SN/Afrom AbstractMemory import * 442381SN/A 452381SN/A# Enum for memory scheduling algorithms, currently First-Come 462381SN/A# First-Served and a First-Row Hit then First-Come First-Served 472982SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 4810405Sandreas.hansson@arm.com 492381SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 502381SN/A# channel, rank, bank, row and column, respectively, and going from 5110405Sandreas.hansson@arm.com# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210405Sandreas.hansson@arm.com# suitable for an open-page policy, optimising for sequential accesses 532381SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5411859Sandreas.hansson@arm.com# maximises parallelism. 5511859Sandreas.hansson@arm.comclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 5610402SN/A 5710405Sandreas.hansson@arm.com# Enum for the page policy, either open, open_adaptive, close, or 5810405Sandreas.hansson@arm.com# close_adaptive. 592381SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 609036SN/A 'close_adaptive'] 6110405Sandreas.hansson@arm.com 6210405Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 6310405Sandreas.hansson@arm.com# that aims to model the most important system-level performance 6410405Sandreas.hansson@arm.com# effects of a DRAM without getting into too much detail of the DRAM 659036SN/A# itself. 6610405Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710405Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810405Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 6910405Sandreas.hansson@arm.com 709036SN/A # single-ported on the system interface side, instantiate with a 7110405Sandreas.hansson@arm.com # bus in front of the controller for multiple ports 722381SN/A port = SlavePort("Slave port") 739031SN/A 749036SN/A # the basic configuration of the controller architecture, note 759036SN/A # that each entry corresponds to a burst for the specific DRAM 768922SN/A # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 7710405Sandreas.hansson@arm.com # the cacheline size or request/packet size 7810405Sandreas.hansson@arm.com write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 799092SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 809715SN/A 819715SN/A # threshold in percent for when to forcefully trigger writes and 8210713Sandreas.hansson@arm.com # start emptying the write buffer 839092SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 849092SN/A 8510405Sandreas.hansson@arm.com # threshold in percentage for when to start writes if the read 8610405Sandreas.hansson@arm.com # queue is empty 8710405Sandreas.hansson@arm.com write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 888922SN/A 8910888Sandreas.hansson@arm.com # minimum write bursts to schedule before switching back to reads 902381SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 919036SN/A "switching to reads") 928922SN/A 939036SN/A # scheduler, address map and page policy 9410405Sandreas.hansson@arm.com mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9510405Sandreas.hansson@arm.com addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 962381SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 9710888Sandreas.hansson@arm.com 9810888Sandreas.hansson@arm.com # enforce a limit on the number of accesses per row 9910888Sandreas.hansson@arm.com max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 1002381SN/A "closing"); 1012381SN/A 10210405Sandreas.hansson@arm.com # size of DRAM Chip in Bytes 10310405Sandreas.hansson@arm.com device_size = Param.MemorySize("Size of DRAM chip") 10410888Sandreas.hansson@arm.com 10510888Sandreas.hansson@arm.com # pipeline latency of the controller and PHY, split into a 1068922SN/A # frontend part and a backend part, with reads and writes serviced 1078922SN/A # by the queues only seeing the frontend contribution, and reads 1088922SN/A # serviced by the memory seeing the sum of the two 1098922SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1108948SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 11110405Sandreas.hansson@arm.com 1128948SN/A # the physical organisation of the DRAM 1138975SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 11410405Sandreas.hansson@arm.com "device/chip") 1158922SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1168948SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 11710405Sandreas.hansson@arm.com "device/chip") 1188948SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1198975SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12010405Sandreas.hansson@arm.com 1218948SN/A # default to 0 bank groups per rank, indicating bank group architecture 1228948SN/A # is not used 12310405Sandreas.hansson@arm.com # update per memory class when bank group architecture is supported 1248948SN/A bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1258922SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 12610405Sandreas.hansson@arm.com # only used for the address mapping as the controller by 1278922SN/A # construction is a single channel and multiple controllers have 1288948SN/A # to be instantiated for a multi-channel configuration 12910405Sandreas.hansson@arm.com channels = Param.Unsigned(1, "Number of channels") 1308948SN/A 1318922SN/A # For power modelling we need to know if the DRAM has a DLL or not 13210405Sandreas.hansson@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 1338922SN/A 1348948SN/A # DRAMPower provides in addition to the core power, the possibility to 13510405Sandreas.hansson@arm.com # include RD/WR termination and IO power. This calculation assumes some 1369036SN/A # default values. The integration of DRAMPower with gem5 does not include 1379090SN/A # IO and RD/WR termination power by default. This might be added as an 13810405Sandreas.hansson@arm.com # additional feature in the future. 1399036SN/A 1409036SN/A # timing behaviour and constraints - all in nanoseconds 1419036SN/A 1429036SN/A # the base clock period of the DRAM 14310405Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 1449036SN/A 14510405Sandreas.hansson@arm.com # the amount of time in nanoseconds from issuing an activate command 1469036SN/A # to the data being available in the row buffer for a read/write 14710405Sandreas.hansson@arm.com tRCD = Param.Latency("RAS to CAS delay") 1489036SN/A 1499036SN/A # the time from issuing a read/write command to seeing the actual data 15010405Sandreas.hansson@arm.com tCL = Param.Latency("CAS latency") 15110405Sandreas.hansson@arm.com 1529036SN/A # minimum time between a precharge and subsequent activate 1539036SN/A tRP = Param.Latency("Row precharge time") 1549036SN/A 15510405Sandreas.hansson@arm.com # minimum time between an activate and a precharge to the same row 15610405Sandreas.hansson@arm.com tRAS = Param.Latency("ACT to PRE delay") 15710405Sandreas.hansson@arm.com 1589036SN/A # minimum time between a write data transfer and a precharge 1599036SN/A tWR = Param.Latency("Write recovery time") 1609036SN/A 1619036SN/A # minimum time between a read and precharge command 1629036SN/A tRTP = Param.Latency("Read to precharge") 1639036SN/A 16410405Sandreas.hansson@arm.com # time to complete a burst transfer, typically the burst length 1659036SN/A # divided by two due to the DDR bus, but by making it a parameter 1669036SN/A # it is easier to also evaluate SDR memories like WideIO. 1679036SN/A # This parameter has to account for burst length. 1689036SN/A # Read/Write requests with data size larger than one full burst are broken 1699036SN/A # down into multiple requests in the controller 1709036SN/A # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 1719036SN/A # With bank group architectures, tBURST represents the CAS-to-CAS 17210405Sandreas.hansson@arm.com # delay for bursts to different bank groups (tCCD_S) 1739036SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1749036SN/A 17510405Sandreas.hansson@arm.com # CAS-to-CAS delay for bursts to the same bank group 1769036SN/A # only utilized with bank group architectures; set to 0 for default case 1779036SN/A # tBURST is equivalent to tCCD_S; no explicit parameter required 17810405Sandreas.hansson@arm.com # for CAS-to-CAS delay for bursts to different bank groups 1799036SN/A tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 1809036SN/A 18110405Sandreas.hansson@arm.com # time taken to complete one refresh cycle (N rows in all banks) 1829036SN/A tRFC = Param.Latency("Refresh cycle time") 1839036SN/A 18410405Sandreas.hansson@arm.com # refresh command interval, how often a "ref" command needs 1859036SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1869036SN/A tREFI = Param.Latency("Refresh command interval") 18710405Sandreas.hansson@arm.com 1889036SN/A # write-to-read, same rank turnaround penalty 1899036SN/A tWTR = Param.Latency("Write to read, same rank switching time") 19010405Sandreas.hansson@arm.com 1919036SN/A # read-to-write, same rank turnaround penalty 1929036SN/A tRTW = Param.Latency("Read to write, same rank switching time") 19310405Sandreas.hansson@arm.com 1949036SN/A # rank-to-rank bus delay penalty 1959036SN/A # this does not correlate to a memory timing parameter and encompasses: 19610405Sandreas.hansson@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 1979036SN/A # different rank bus delay 19810405Sandreas.hansson@arm.com tCS = Param.Latency("Rank to rank switching time") 1999036SN/A 2009036SN/A # minimum row activate to row activate delay time 20110405Sandreas.hansson@arm.com tRRD = Param.Latency("ACT to ACT delay") 20210713Sandreas.hansson@arm.com 20310713Sandreas.hansson@arm.com # only utilized with bank group architectures; set to 0 for default case 2048922SN/A tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 2058922SN/A 2068922SN/A # time window in which a maximum number of activates are allowed 2079716SN/A # to take place, set to 0 to disable 2089716SN/A tXAW = Param.Latency("X activation window") 2099716SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2109716SN/A 2119716SN/A # time to exit power-down mode 2129716SN/A # Exit power-down to next valid command delay 2139716SN/A tXP = Param.Latency("0ns", "Power-up Delay") 2149716SN/A 2159716SN/A # Exit Powerdown to commands requiring a locked DLL 2169716SN/A tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 2179716SN/A 21810888Sandreas.hansson@arm.com # time to exit self-refresh mode 2199716SN/A tXS = Param.Latency("0ns", "Self-refresh exit latency") 2209716SN/A 2219716SN/A # time to exit self-refresh mode with locked DLL 2229716SN/A tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 2239716SN/A 2249716SN/A # Currently rolled into other params 22510888Sandreas.hansson@arm.com ###################################################################### 22610405Sandreas.hansson@arm.com 2279778SN/A # tRC - assumed to be tRAS + tRP 2289716SN/A 2299716SN/A # Power Behaviour and Constraints 2309716SN/A # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 2319716SN/A # defined as VDD and VDD2. Each current is defined for each voltage domain 2329716SN/A # separately. For example, current IDD0 is active-precharge current for 23310713Sandreas.hansson@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 23410713Sandreas.hansson@arm.com # voltage domain VDD2. 23510713Sandreas.hansson@arm.com # By default all currents are set to 0mA. Users who are only interested in 2369716SN/A # the performance of DRAMs can leave them at 0. 2379716SN/A 2389716SN/A # Operating 1 Bank Active-Precharge current 2399716SN/A IDD0 = Param.Current("0mA", "Active precharge current") 2409716SN/A 24110713Sandreas.hansson@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 2429716SN/A IDD02 = Param.Current("0mA", "Active precharge current VDD2") 2439716SN/A 2449716SN/A # Precharge Power-down Current: Slow exit 2459716SN/A IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 2469716SN/A 2479716SN/A # Precharge Power-down Current: Slow exit multiple voltage Range 2489716SN/A IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 2499716SN/A 2509716SN/A # Precharge Power-down Current: Fast exit 2519716SN/A IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 2529716SN/A 2539716SN/A # Precharge Power-down Current: Fast exit multiple voltage Range 2549716SN/A IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 2559716SN/A 25610888Sandreas.hansson@arm.com # Precharge Standby current 2574475SN/A IDD2N = Param.Current("0mA", "Precharge Standby current") 2588948SN/A 25910656Sandreas.hansson@arm.com # Precharge Standby current multiple voltage range 26010656Sandreas.hansson@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 26110656Sandreas.hansson@arm.com 2628948SN/A # Active Power-down current: slow exit 26311168Sandreas.hansson@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 2648948SN/A 2659524SN/A # Active Power-down current: slow exit multiple voltage range 2669524SN/A IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 2679524SN/A 2689524SN/A # Active Power-down current : fast exit 2699524SN/A IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 2709524SN/A 27110402SN/A # Active Power-down current : fast exit multiple voltage range 27210402SN/A IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 27310402SN/A 27410402SN/A # Active Standby current 27510719SMarco.Balboni@ARM.com IDD3N = Param.Current("0mA", "Active Standby current") 27610719SMarco.Balboni@ARM.com 27710719SMarco.Balboni@ARM.com # Active Standby current multiple voltage range 27811334Sandreas.hansson@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 27911334Sandreas.hansson@arm.com 28011334Sandreas.hansson@arm.com # Burst Read Operating Current 28112341Snikos.nikoleris@arm.com IDD4R = Param.Current("0mA", "READ current") 28212341Snikos.nikoleris@arm.com 28312341Snikos.nikoleris@arm.com # Burst Read Operating Current multiple voltage range 28410883Sali.jafri@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 28511190Sandreas.hansson@arm.com 28611190Sandreas.hansson@arm.com # Burst Write Operating Current 28710883Sali.jafri@arm.com IDD4W = Param.Current("0mA", "WRITE current") 28811190Sandreas.hansson@arm.com 28910883Sali.jafri@arm.com # Burst Write Operating Current multiple voltage range 29010405Sandreas.hansson@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 2918975SN/A 2929945SN/A # Refresh Current 2938975SN/A IDD5 = Param.Current("0mA", "Refresh current") 29410405Sandreas.hansson@arm.com 2958975SN/A # Refresh Current multiple voltage range 2969945SN/A IDD52 = Param.Current("0mA", "Refresh current VDD2") 2974475SN/A 29810405Sandreas.hansson@arm.com # Self-Refresh Current 2998975SN/A IDD6 = Param.Current("0mA", "Self-refresh Current") 3009945SN/A 3018975SN/A # Self-Refresh Current multiple voltage range 30210405Sandreas.hansson@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 3038975SN/A 3049945SN/A # Main voltage range of the DRAM 3058948SN/A VDD = Param.Voltage("0V", "Main Voltage Range") 3069092SN/A 3079092SN/A # Second voltage range defined by some DRAMs 30810713Sandreas.hansson@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 3099092SN/A 3108948SN/A# A single DDR3-1600 x64 channel (one command and address bus), with 3118948SN/A# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 3128948SN/A# an 8x8 configuration. 3138948SN/Aclass DDR3_1600_x64(DRAMCtrl): 3148948SN/A # size of device in bytes 3158948SN/A device_size = '512MB' 3168948SN/A 3178948SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 31810402SN/A device_bus_width = 8 31910402SN/A 32010402SN/A # DDR3 is a BL8 device 32110402SN/A burst_length = 8 32210402SN/A 32310402SN/A # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 32410402SN/A device_rowbuffer_size = '1kB' 32510402SN/A 32610402SN/A # 8x8 configuration, so 8 devices 32710402SN/A devices_per_rank = 8 32810402SN/A 32910402SN/A # Use two ranks 33010402SN/A ranks_per_channel = 2 33110402SN/A 33210888Sandreas.hansson@arm.com # DDR3 has 8 banks in all configurations 3338948SN/A banks_per_rank = 8 33410405Sandreas.hansson@arm.com 3354475SN/A # 800 MHz 3369032SN/A tCK = '1.25ns' 3374475SN/A 33810405Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 3398948SN/A tBURST = '5ns' 3409032SN/A 3418948SN/A # DDR3-1600 11-11-11 3428948SN/A tRCD = '13.75ns' 3438948SN/A tCL = '13.75ns' 3448948SN/A tRP = '13.75ns' 3458948SN/A tRAS = '35ns' 3468948SN/A tRRD = '6ns' 3478948SN/A tXAW = '30ns' 3488948SN/A activation_limit = 4 3498948SN/A tRFC = '260ns' 3508948SN/A 3518948SN/A tWR = '15ns' 3528948SN/A 35310402SN/A # Greater of 4 CK or 7.5 ns 35410402SN/A tWTR = '7.5ns' 35510888Sandreas.hansson@arm.com 35610888Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35710402SN/A tRTP = '7.5ns' 35810402SN/A 35910402SN/A # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 36010402SN/A tRTW = '2.5ns' 36110402SN/A 36210402SN/A # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 36310402SN/A tCS = '2.5ns' 36410402SN/A 36510402SN/A # <=85C, half for >85C 36610402SN/A tREFI = '7.8us' 36710402SN/A 36810402SN/A # Current values from datasheet 36910402SN/A IDD0 = '75mA' 37010402SN/A IDD2N = '50mA' 37110402SN/A IDD3N = '57mA' 37210402SN/A IDD4W = '165mA' 37310402SN/A IDD4R = '187mA' 37410888Sandreas.hansson@arm.com IDD5 = '220mA' 37510888Sandreas.hansson@arm.com VDD = '1.5V' 3768948SN/A 37710405Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 3784475SN/A# options for the DDR-1600 configuration, based on the same DDR3-1600 3799032SN/A# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 3804475SN/A# consistent across the two configurations. 38110405Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 3828948SN/A # 1066 MHz 3839032SN/A tCK = '0.938ns' 3848948SN/A 3858948SN/A # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 3868948SN/A tBURST = '3.752ns' 3878948SN/A 3888948SN/A # DDR3-2133 14-14-14 3898948SN/A tRCD = '13.09ns' 3908948SN/A tCL = '13.09ns' 3918948SN/A tRP = '13.09ns' 3928948SN/A tRAS = '33ns' 3939031SN/A tRRD = '5ns' 3948948SN/A tXAW = '25ns' 39511334Sandreas.hansson@arm.com 39611334Sandreas.hansson@arm.com # Current values from datasheet 39711334Sandreas.hansson@arm.com IDD0 = '70mA' 39811334Sandreas.hansson@arm.com IDD2N = '37mA' 39911334Sandreas.hansson@arm.com IDD3N = '44mA' 40011334Sandreas.hansson@arm.com IDD4W = '157mA' 40110405Sandreas.hansson@arm.com IDD4R = '191mA' 40211564Sdavid.guillen@arm.com IDD5 = '250mA' 40310401SN/A VDD = '1.5V' 4049712SN/A 4052381SN/A# A single DDR4-2400 x64 channel (one command and address bus), with 4062381SN/A# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 4079036SN/A# in an 8x8 configuration. 4082568SN/Aclass DDR4_2400_x64(DRAMCtrl): 40910405Sandreas.hansson@arm.com # size of device 4109092SN/A device_size = '512MB' 41110405Sandreas.hansson@arm.com 4129715SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 4139712SN/A device_bus_width = 8 4142381SN/A 4152381SN/A # DDR4 is a BL8 device 41610405Sandreas.hansson@arm.com burst_length = 8 417 418 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 419 device_rowbuffer_size = '1kB' 420 421 # 8x8 configuration, so 8 devices 422 devices_per_rank = 8 423 424 # Match our DDR3 configurations which is dual rank 425 ranks_per_channel = 2 426 427 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 428 # Set to 4 for x4, x8 case 429 bank_groups_per_rank = 4 430 431 # DDR4 has 16 banks (4 bank groups) in all 432 # configurations. Currently we do not capture the additional 433 # constraints incurred by the bank groups 434 banks_per_rank = 16 435 436 # 1200 MHz 437 tCK = '0.833ns' 438 439 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 440 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 441 # With bank group architectures, tBURST represents the CAS-to-CAS 442 # delay for bursts to different bank groups (tCCD_S) 443 tBURST = '3.333ns' 444 445 # @2400 data rate, tCCD_L is 6 CK 446 # CAS-to-CAS delay for bursts to the same bank group 447 # tBURST is equivalent to tCCD_S; no explicit parameter required 448 # for CAS-to-CAS delay for bursts to different bank groups 449 tCCD_L = '5ns'; 450 451 # DDR4-2400 17-17-17 452 tRCD = '14.16ns' 453 tCL = '14.16ns' 454 tRP = '14.16ns' 455 tRAS = '32ns' 456 457 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 458 tRRD = '3.3ns' 459 460 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 461 tRRD_L = '4.9ns'; 462 463 tXAW = '21ns' 464 activation_limit = 4 465 tRFC = '350ns' 466 467 tWR = '15ns' 468 469 # Here using the average of WTR_S and WTR_L 470 tWTR = '5ns' 471 472 # Greater of 4 CK or 7.5 ns 473 tRTP = '7.5ns' 474 475 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 476 tRTW = '1.666ns' 477 478 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 479 tCS = '1.666ns' 480 481 # <=85C, half for >85C 482 tREFI = '7.8us' 483 484 # Current values from datasheet 485 IDD0 = '64mA' 486 IDD02 = '4mA' 487 IDD2N = '50mA' 488 IDD3N = '67mA' 489 IDD3N2 = '3mA' 490 IDD4W = '180mA' 491 IDD4R = '160mA' 492 IDD5 = '192mA' 493 VDD = '1.2V' 494 VDD2 = '2.5V' 495 496# A single LPDDR2-S4 x32 interface (one command/address bus), with 497# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 498# in a 1x32 configuration. 499class LPDDR2_S4_1066_x32(DRAMCtrl): 500 # No DLL in LPDDR2 501 dll = False 502 503 # size of device 504 device_size = '512MB' 505 506 # 1x32 configuration, 1 device with a 32-bit interface 507 device_bus_width = 32 508 509 # LPDDR2_S4 is a BL4 and BL8 device 510 burst_length = 8 511 512 # Each device has a page (row buffer) size of 1KB 513 # (this depends on the memory density) 514 device_rowbuffer_size = '1kB' 515 516 # 1x32 configuration, so 1 device 517 devices_per_rank = 1 518 519 # Use a single rank 520 ranks_per_channel = 1 521 522 # LPDDR2-S4 has 8 banks in all configurations 523 banks_per_rank = 8 524 525 # 533 MHz 526 tCK = '1.876ns' 527 528 # Fixed at 15 ns 529 tRCD = '15ns' 530 531 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 532 tCL = '15ns' 533 534 # Pre-charge one bank 15 ns (all banks 18 ns) 535 tRP = '15ns' 536 537 tRAS = '42ns' 538 tWR = '15ns' 539 540 tRTP = '7.5ns' 541 542 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 543 # Note this is a BL8 DDR device. 544 # Requests larger than 32 bytes are broken down into multiple requests 545 # in the controller 546 tBURST = '7.5ns' 547 548 # LPDDR2-S4, 4 Gbit 549 tRFC = '130ns' 550 tREFI = '3.9us' 551 552 # Irrespective of speed grade, tWTR is 7.5 ns 553 tWTR = '7.5ns' 554 555 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 556 tRTW = '3.75ns' 557 558 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 559 tCS = '3.75ns' 560 561 # Activate to activate irrespective of density and speed grade 562 tRRD = '10.0ns' 563 564 # Irrespective of density, tFAW is 50 ns 565 tXAW = '50ns' 566 activation_limit = 4 567 568 # Current values from datasheet 569 IDD0 = '15mA' 570 IDD02 = '70mA' 571 IDD2N = '2mA' 572 IDD2N2 = '30mA' 573 IDD3N = '2.5mA' 574 IDD3N2 = '30mA' 575 IDD4W = '10mA' 576 IDD4W2 = '190mA' 577 IDD4R = '3mA' 578 IDD4R2 = '220mA' 579 IDD5 = '40mA' 580 IDD52 = '150mA' 581 VDD = '1.8V' 582 VDD2 = '1.2V' 583 584# A single WideIO x128 interface (one command and address bus), with 585# default timings based on an estimated WIO-200 8 Gbit part. 586class WideIO_200_x128(DRAMCtrl): 587 # No DLL for WideIO 588 dll = False 589 590 # size of device 591 device_size = '1024MB' 592 593 # 1x128 configuration, 1 device with a 128-bit interface 594 device_bus_width = 128 595 596 # This is a BL4 device 597 burst_length = 4 598 599 # Each device has a page (row buffer) size of 4KB 600 # (this depends on the memory density) 601 device_rowbuffer_size = '4kB' 602 603 # 1x128 configuration, so 1 device 604 devices_per_rank = 1 605 606 # Use one rank for a one-high die stack 607 ranks_per_channel = 1 608 609 # WideIO has 4 banks in all configurations 610 banks_per_rank = 4 611 612 # 200 MHz 613 tCK = '5ns' 614 615 # WIO-200 616 tRCD = '18ns' 617 tCL = '18ns' 618 tRP = '18ns' 619 tRAS = '42ns' 620 tWR = '15ns' 621 # Read to precharge is same as the burst 622 tRTP = '20ns' 623 624 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 625 # Note this is a BL4 SDR device. 626 tBURST = '20ns' 627 628 # WIO 8 Gb 629 tRFC = '210ns' 630 631 # WIO 8 Gb, <=85C, half for >85C 632 tREFI = '3.9us' 633 634 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 635 tWTR = '15ns' 636 637 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 638 tRTW = '10ns' 639 640 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 641 tCS = '10ns' 642 643 # Activate to activate irrespective of density and speed grade 644 tRRD = '10.0ns' 645 646 # Two instead of four activation window 647 tXAW = '50ns' 648 activation_limit = 2 649 650 # The WideIO specification does not provide current information 651 652# A single LPDDR3 x32 interface (one command/address bus), with 653# default timings based on a LPDDR3-1600 4 Gbit part (Micron 654# EDF8132A1MC) in a 1x32 configuration. 655class LPDDR3_1600_x32(DRAMCtrl): 656 # No DLL for LPDDR3 657 dll = False 658 659 # size of device 660 device_size = '512MB' 661 662 # 1x32 configuration, 1 device with a 32-bit interface 663 device_bus_width = 32 664 665 # LPDDR3 is a BL8 device 666 burst_length = 8 667 668 # Each device has a page (row buffer) size of 4KB 669 device_rowbuffer_size = '4kB' 670 671 # 1x32 configuration, so 1 device 672 devices_per_rank = 1 673 674 # Technically the datasheet is a dual-rank package, but for 675 # comparison with the LPDDR2 config we stick to a single rank 676 ranks_per_channel = 1 677 678 # LPDDR3 has 8 banks in all configurations 679 banks_per_rank = 8 680 681 # 800 MHz 682 tCK = '1.25ns' 683 684 tRCD = '18ns' 685 686 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 687 tCL = '15ns' 688 689 tRAS = '42ns' 690 tWR = '15ns' 691 692 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 693 tRTP = '7.5ns' 694 695 # Pre-charge one bank 18 ns (all banks 21 ns) 696 tRP = '18ns' 697 698 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 699 # Note this is a BL8 DDR device. 700 # Requests larger than 32 bytes are broken down into multiple requests 701 # in the controller 702 tBURST = '5ns' 703 704 # LPDDR3, 4 Gb 705 tRFC = '130ns' 706 tREFI = '3.9us' 707 708 # Irrespective of speed grade, tWTR is 7.5 ns 709 tWTR = '7.5ns' 710 711 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 712 tRTW = '2.5ns' 713 714 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 715 tCS = '2.5ns' 716 717 # Activate to activate irrespective of density and speed grade 718 tRRD = '10.0ns' 719 720 # Irrespective of size, tFAW is 50 ns 721 tXAW = '50ns' 722 activation_limit = 4 723 724 # Current values from datasheet 725 IDD0 = '8mA' 726 IDD02 = '60mA' 727 IDD2N = '0.8mA' 728 IDD2N2 = '26mA' 729 IDD3N = '2mA' 730 IDD3N2 = '34mA' 731 IDD4W = '2mA' 732 IDD4W2 = '190mA' 733 IDD4R = '2mA' 734 IDD4R2 = '230mA' 735 IDD5 = '28mA' 736 IDD52 = '150mA' 737 VDD = '1.8V' 738 VDD2 = '1.2V' 739