DRAMCtrl.py revision 10489:99d59caa4c8f
1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
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32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40#          Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60                                'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67    type = 'DRAMCtrl'
68    cxx_header = "mem/dram_ctrl.hh"
69
70    # single-ported on the system interface side, instantiate with a
71    # bus in front of the controller for multiple ports
72    port = SlavePort("Slave port")
73
74    # the basic configuration of the controller architecture
75    write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76    read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78    # threshold in percent for when to forcefully trigger writes and
79    # start emptying the write buffer
80    write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82    # threshold in percentage for when to start writes if the read
83    # queue is empty
84    write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86    # minimum write bursts to schedule before switching back to reads
87    min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88                                           "switching to reads")
89
90    # scheduler, address map and page policy
91    mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92    addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93    page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95    # enforce a limit on the number of accesses per row
96    max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97                                          "closing");
98
99    # size of DRAM Chip in Bytes
100    device_size = Param.MemorySize("Size of DRAM chip")
101
102    # pipeline latency of the controller and PHY, split into a
103    # frontend part and a backend part, with reads and writes serviced
104    # by the queues only seeing the frontend contribution, and reads
105    # serviced by the memory seeing the sum of the two
106    static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
107    static_backend_latency = Param.Latency("10ns", "Static backend latency")
108
109    # the physical organisation of the DRAM
110    device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
111                                      "device/chip")
112    burst_length = Param.Unsigned("Burst lenght (BL) in beats")
113    device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
114                                           "device/chip")
115    devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
116    ranks_per_channel = Param.Unsigned("Number of ranks per channel")
117
118    # default to 0 bank groups per rank, indicating bank group architecture
119    # is not used
120    # update per memory class when bank group architecture is supported
121    bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
122    banks_per_rank = Param.Unsigned("Number of banks per rank")
123    # only used for the address mapping as the controller by
124    # construction is a single channel and multiple controllers have
125    # to be instantiated for a multi-channel configuration
126    channels = Param.Unsigned(1, "Number of channels")
127
128    # For power modelling we need to know if the DRAM has a DLL or not
129    dll = Param.Bool(True, "DRAM has DLL or not")
130
131    # DRAMPower provides in addition to the core power, the possibility to
132    # include RD/WR termination and IO power. This calculation assumes some
133    # default values. The integration of DRAMPower with gem5 does not include
134    # IO and RD/WR termination power by default. This might be added as an
135    # additional feature in the future.
136
137    # timing behaviour and constraints - all in nanoseconds
138
139    # the base clock period of the DRAM
140    tCK = Param.Latency("Clock period")
141
142    # the amount of time in nanoseconds from issuing an activate command
143    # to the data being available in the row buffer for a read/write
144    tRCD = Param.Latency("RAS to CAS delay")
145
146    # the time from issuing a read/write command to seeing the actual data
147    tCL = Param.Latency("CAS latency")
148
149    # minimum time between a precharge and subsequent activate
150    tRP = Param.Latency("Row precharge time")
151
152    # minimum time between an activate and a precharge to the same row
153    tRAS = Param.Latency("ACT to PRE delay")
154
155    # minimum time between a write data transfer and a precharge
156    tWR = Param.Latency("Write recovery time")
157
158    # minimum time between a read and precharge command
159    tRTP = Param.Latency("Read to precharge")
160
161    # time to complete a burst transfer, typically the burst length
162    # divided by two due to the DDR bus, but by making it a parameter
163    # it is easier to also evaluate SDR memories like WideIO.
164    # This parameter has to account for burst length.
165    # Read/Write requests with data size larger than one full burst are broken
166    # down into multiple requests in the controller
167    # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
168    # With bank group architectures, tBURST represents the CAS-to-CAS
169    # delay for bursts to different bank groups (tCCD_S)
170    tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
171
172    # CAS-to-CAS delay for bursts to the same bank group
173    # only utilized with bank group architectures; set to 0 for default case
174    # tBURST is equivalent to tCCD_S; no explicit parameter required
175    # for CAS-to-CAS delay for bursts to different bank groups
176    tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
177
178    # time taken to complete one refresh cycle (N rows in all banks)
179    tRFC = Param.Latency("Refresh cycle time")
180
181    # refresh command interval, how often a "ref" command needs
182    # to be sent. It is 7.8 us for a 64ms refresh requirement
183    tREFI = Param.Latency("Refresh command interval")
184
185    # write-to-read, same rank turnaround penalty
186    tWTR = Param.Latency("Write to read, same rank switching time")
187
188    # read-to-write, same rank turnaround penalty
189    tRTW = Param.Latency("Read to write, same rank switching time")
190
191    # rank-to-rank bus delay penalty
192    # this does not correlate to a memory timing parameter and encompasses:
193    # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
194    # different rank bus delay
195    tCS = Param.Latency("Rank to rank switching time")
196
197    # minimum row activate to row activate delay time
198    tRRD = Param.Latency("ACT to ACT delay")
199
200    # only utilized with bank group architectures; set to 0 for default case
201    tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
202
203    # time window in which a maximum number of activates are allowed
204    # to take place, set to 0 to disable
205    tXAW = Param.Latency("X activation window")
206    activation_limit = Param.Unsigned("Max number of activates in window")
207
208    # time to exit power-down mode
209    # Exit power-down to next valid command delay
210    tXP = Param.Latency("0ns", "Power-up Delay")
211
212    # Exit Powerdown to commands requiring a locked DLL
213    tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
214
215    # time to exit self-refresh mode
216    tXS = Param.Latency("0ns", "Self-refresh exit latency")
217
218    # time to exit self-refresh mode with locked DLL
219    tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
220
221    # Currently rolled into other params
222    ######################################################################
223
224    # tRC  - assumed to be tRAS + tRP
225
226    # Power Behaviour and Constraints
227    # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
228    # defined as VDD and VDD2. Each current is defined for each voltage domain
229    # separately. For example, current IDD0 is active-precharge current for
230    # voltage domain VDD and current IDD02 is active-precharge current for
231    # voltage domain VDD2.
232    # By default all currents are set to 0mA. Users who are only interested in
233    # the performance of DRAMs can leave them at 0.
234
235    # Operating 1 Bank Active-Precharge current
236    IDD0 = Param.Current("0mA", "Active precharge current")
237
238    # Operating 1 Bank Active-Precharge current multiple voltage Range
239    IDD02 = Param.Current("0mA", "Active precharge current VDD2")
240
241    # Precharge Power-down Current: Slow exit
242    IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
243
244    # Precharge Power-down Current: Slow exit multiple voltage Range
245    IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
246
247    # Precharge Power-down Current: Fast exit
248    IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
249
250    # Precharge Power-down Current: Fast exit multiple voltage Range
251    IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
252
253    # Precharge Standby current
254    IDD2N = Param.Current("0mA", "Precharge Standby current")
255
256    # Precharge Standby current multiple voltage range
257    IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
258
259    # Active Power-down current: slow exit
260    IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
261
262    # Active Power-down current: slow exit multiple voltage range
263    IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
264
265    # Active Power-down current : fast exit
266    IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
267
268    # Active Power-down current : fast exit multiple voltage range
269    IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
270
271    # Active Standby current
272    IDD3N = Param.Current("0mA", "Active Standby current")
273
274    # Active Standby current multiple voltage range
275    IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
276
277    # Burst Read Operating Current
278    IDD4R = Param.Current("0mA", "READ current")
279
280    # Burst Read Operating Current multiple voltage range
281    IDD4R2 = Param.Current("0mA", "READ current VDD2")
282
283    # Burst Write Operating Current
284    IDD4W = Param.Current("0mA", "WRITE current")
285
286    # Burst Write Operating Current multiple voltage range
287    IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
288
289    # Refresh Current
290    IDD5 = Param.Current("0mA", "Refresh current")
291
292    # Refresh Current multiple voltage range
293    IDD52 = Param.Current("0mA", "Refresh current VDD2")
294
295    # Self-Refresh Current
296    IDD6 = Param.Current("0mA", "Self-refresh Current")
297
298    # Self-Refresh Current multiple voltage range
299    IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
300
301    # Main voltage range of the DRAM
302    VDD = Param.Voltage("0V", "Main Voltage Range")
303
304    # Second voltage range defined by some DRAMs
305    VDD2 = Param.Voltage("0V", "2nd Voltage Range")
306
307# A single DDR3-1600 x64 channel (one command and address bus), with
308# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
309# an 8x8 configuration.
310class DDR3_1600_x64(DRAMCtrl):
311    # size of device in bytes
312    device_size = '512MB'
313
314    # 8x8 configuration, 8 devices each with an 8-bit interface
315    device_bus_width = 8
316
317    # DDR3 is a BL8 device
318    burst_length = 8
319
320    # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
321    device_rowbuffer_size = '1kB'
322
323    # 8x8 configuration, so 8 devices
324    devices_per_rank = 8
325
326    # Use two ranks
327    ranks_per_channel = 2
328
329    # DDR3 has 8 banks in all configurations
330    banks_per_rank = 8
331
332    # 800 MHz
333    tCK = '1.25ns'
334
335    # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
336    tBURST = '5ns'
337
338    # DDR3-1600 11-11-11
339    tRCD = '13.75ns'
340    tCL = '13.75ns'
341    tRP = '13.75ns'
342    tRAS = '35ns'
343    tRRD = '6ns'
344    tXAW = '30ns'
345    activation_limit = 4
346    tRFC = '260ns'
347
348    tWR = '15ns'
349
350    # Greater of 4 CK or 7.5 ns
351    tWTR = '7.5ns'
352
353    # Greater of 4 CK or 7.5 ns
354    tRTP = '7.5ns'
355
356    # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
357    tRTW = '2.5ns'
358
359    # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
360    tCS = '2.5ns'
361
362    # <=85C, half for >85C
363    tREFI = '7.8us'
364
365    # Current values from datasheet
366    IDD0 = '75mA'
367    IDD2N = '50mA'
368    IDD3N = '57mA'
369    IDD4W = '165mA'
370    IDD4R = '187mA'
371    IDD5 = '220mA'
372    VDD = '1.5V'
373
374# A single DDR3-2133 x64 channel refining a selected subset of the
375# options for the DDR-1600 configuration, based on the same DDR3-1600
376# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
377# consistent across the two configurations.
378class DDR3_2133_x64(DDR3_1600_x64):
379    # 1066 MHz
380    tCK = '0.938ns'
381
382    # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
383    tBURST = '3.752ns'
384
385    # DDR3-2133 14-14-14
386    tRCD = '13.09ns'
387    tCL = '13.09ns'
388    tRP = '13.09ns'
389    tRAS = '33ns'
390    tRRD = '5ns'
391    tXAW = '25ns'
392
393    # Current values from datasheet
394    IDD0 = '70mA'
395    IDD2N = '37mA'
396    IDD3N = '44mA'
397    IDD4W = '157mA'
398    IDD4R = '191mA'
399    IDD5 = '250mA'
400    VDD = '1.5V'
401
402# A single DDR4-2400 x64 channel (one command and address bus), with
403# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
404# in an 8x8 configuration.
405class DDR4_2400_x64(DRAMCtrl):
406    # size of device
407    device_size = '512MB'
408
409    # 8x8 configuration, 8 devices each with an 8-bit interface
410    device_bus_width = 8
411
412    # DDR4 is a BL8 device
413    burst_length = 8
414
415    # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
416    device_rowbuffer_size = '1kB'
417
418    # 8x8 configuration, so 8 devices
419    devices_per_rank = 8
420
421    # Match our DDR3 configurations which is dual rank
422    ranks_per_channel = 2
423
424    # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
425    # Set to 4 for x4, x8 case
426    bank_groups_per_rank = 4
427
428    # DDR4 has 16 banks (4 bank groups) in all
429    # configurations. Currently we do not capture the additional
430    # constraints incurred by the bank groups
431    banks_per_rank = 16
432
433    # 1200 MHz
434    tCK = '0.833ns'
435
436    # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
437    # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
438    # With bank group architectures, tBURST represents the CAS-to-CAS
439    # delay for bursts to different bank groups (tCCD_S)
440    tBURST = '3.333ns'
441
442    # @2400 data rate, tCCD_L is 6 CK
443    # CAS-to-CAS delay for bursts to the same bank group
444    # tBURST is equivalent to tCCD_S; no explicit parameter required
445    # for CAS-to-CAS delay for bursts to different bank groups
446    tCCD_L = '5ns';
447
448    # DDR4-2400 17-17-17
449    tRCD = '14.16ns'
450    tCL = '14.16ns'
451    tRP = '14.16ns'
452    tRAS = '32ns'
453
454    # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
455    tRRD = '3.3ns'
456
457    # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
458    tRRD_L = '4.9ns';
459
460    tXAW = '21ns'
461    activation_limit = 4
462    tRFC = '350ns'
463
464    tWR = '15ns'
465
466    # Here using the average of WTR_S and WTR_L
467    tWTR = '5ns'
468
469    # Greater of 4 CK or 7.5 ns
470    tRTP = '7.5ns'
471
472    # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
473    tRTW = '1.666ns'
474
475    # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
476    tCS = '1.666ns'
477
478    # <=85C, half for >85C
479    tREFI = '7.8us'
480
481    # Current values from datasheet
482    IDD0 = '64mA'
483    IDD02 = '4mA'
484    IDD2N = '50mA'
485    IDD3N = '67mA'
486    IDD3N2 = '3mA'
487    IDD4W = '180mA'
488    IDD4R = '160mA'
489    IDD5 = '192mA'
490    VDD = '1.2V'
491    VDD2 = '2.5V'
492
493# A single LPDDR2-S4 x32 interface (one command/address bus), with
494# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
495# in a 1x32 configuration.
496class LPDDR2_S4_1066_x32(DRAMCtrl):
497    # No DLL in LPDDR2
498    dll = False
499
500    # size of device
501    device_size = '512MB'
502
503    # 1x32 configuration, 1 device with a 32-bit interface
504    device_bus_width = 32
505
506    # LPDDR2_S4 is a BL4 and BL8 device
507    burst_length = 8
508
509    # Each device has a page (row buffer) size of 1KB
510    # (this depends on the memory density)
511    device_rowbuffer_size = '1kB'
512
513    # 1x32 configuration, so 1 device
514    devices_per_rank = 1
515
516    # Use a single rank
517    ranks_per_channel = 1
518
519    # LPDDR2-S4 has 8 banks in all configurations
520    banks_per_rank = 8
521
522    # 533 MHz
523    tCK = '1.876ns'
524
525    # Fixed at 15 ns
526    tRCD = '15ns'
527
528    # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
529    tCL = '15ns'
530
531    # Pre-charge one bank 15 ns (all banks 18 ns)
532    tRP = '15ns'
533
534    tRAS = '42ns'
535    tWR = '15ns'
536
537    tRTP = '7.5ns'
538
539    # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
540    # Note this is a BL8 DDR device.
541    # Requests larger than 32 bytes are broken down into multiple requests
542    # in the controller
543    tBURST = '7.5ns'
544
545    # LPDDR2-S4, 4 Gbit
546    tRFC = '130ns'
547    tREFI = '3.9us'
548
549    # Irrespective of speed grade, tWTR is 7.5 ns
550    tWTR = '7.5ns'
551
552    # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
553    tRTW = '3.75ns'
554
555    # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
556    tCS = '3.75ns'
557
558    # Activate to activate irrespective of density and speed grade
559    tRRD = '10.0ns'
560
561    # Irrespective of density, tFAW is 50 ns
562    tXAW = '50ns'
563    activation_limit = 4
564
565    # Current values from datasheet
566    IDD0 = '15mA'
567    IDD02 = '70mA'
568    IDD2N = '2mA'
569    IDD2N2 = '30mA'
570    IDD3N = '2.5mA'
571    IDD3N2 = '30mA'
572    IDD4W = '10mA'
573    IDD4W2 = '190mA'
574    IDD4R = '3mA'
575    IDD4R2 = '220mA'
576    IDD5 = '40mA'
577    IDD52 = '150mA'
578    VDD = '1.8V'
579    VDD2 = '1.2V'
580
581# A single WideIO x128 interface (one command and address bus), with
582# default timings based on an estimated WIO-200 8 Gbit part.
583class WideIO_200_x128(DRAMCtrl):
584    # No DLL for WideIO
585    dll = False
586
587    # size of device
588    device_size = '1024MB'
589
590    # 1x128 configuration, 1 device with a 128-bit interface
591    device_bus_width = 128
592
593    # This is a BL4 device
594    burst_length = 4
595
596    # Each device has a page (row buffer) size of 4KB
597    # (this depends on the memory density)
598    device_rowbuffer_size = '4kB'
599
600    # 1x128 configuration, so 1 device
601    devices_per_rank = 1
602
603    # Use one rank for a one-high die stack
604    ranks_per_channel = 1
605
606    # WideIO has 4 banks in all configurations
607    banks_per_rank = 4
608
609    # 200 MHz
610    tCK = '5ns'
611
612    # WIO-200
613    tRCD = '18ns'
614    tCL = '18ns'
615    tRP = '18ns'
616    tRAS = '42ns'
617    tWR = '15ns'
618    # Read to precharge is same as the burst
619    tRTP = '20ns'
620
621    # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
622    # Note this is a BL4 SDR device.
623    tBURST = '20ns'
624
625    # WIO 8 Gb
626    tRFC = '210ns'
627
628    # WIO 8 Gb, <=85C, half for >85C
629    tREFI = '3.9us'
630
631    # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
632    tWTR = '15ns'
633
634    # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
635    tRTW = '10ns'
636
637    # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
638    tCS = '10ns'
639
640    # Activate to activate irrespective of density and speed grade
641    tRRD = '10.0ns'
642
643    # Two instead of four activation window
644    tXAW = '50ns'
645    activation_limit = 2
646
647    # The WideIO specification does not provide current information
648
649# A single LPDDR3 x32 interface (one command/address bus), with
650# default timings based on a LPDDR3-1600 4 Gbit part (Micron
651# EDF8132A1MC) in a 1x32 configuration.
652class LPDDR3_1600_x32(DRAMCtrl):
653    # No DLL for LPDDR3
654    dll = False
655
656    # size of device
657    device_size = '512MB'
658
659    # 1x32 configuration, 1 device with a 32-bit interface
660    device_bus_width = 32
661
662    # LPDDR3 is a BL8 device
663    burst_length = 8
664
665    # Each device has a page (row buffer) size of 4KB
666    device_rowbuffer_size = '4kB'
667
668    # 1x32 configuration, so 1 device
669    devices_per_rank = 1
670
671    # Technically the datasheet is a dual-rank package, but for
672    # comparison with the LPDDR2 config we stick to a single rank
673    ranks_per_channel = 1
674
675    # LPDDR3 has 8 banks in all configurations
676    banks_per_rank = 8
677
678    # 800 MHz
679    tCK = '1.25ns'
680
681    tRCD = '18ns'
682
683    # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
684    tCL = '15ns'
685
686    tRAS = '42ns'
687    tWR = '15ns'
688
689    # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
690    tRTP = '7.5ns'
691
692    # Pre-charge one bank 18 ns (all banks 21 ns)
693    tRP = '18ns'
694
695    # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
696    # Note this is a BL8 DDR device.
697    # Requests larger than 32 bytes are broken down into multiple requests
698    # in the controller
699    tBURST = '5ns'
700
701    # LPDDR3, 4 Gb
702    tRFC = '130ns'
703    tREFI = '3.9us'
704
705    # Irrespective of speed grade, tWTR is 7.5 ns
706    tWTR = '7.5ns'
707
708    # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
709    tRTW = '2.5ns'
710
711    # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
712    tCS = '2.5ns'
713
714    # Activate to activate irrespective of density and speed grade
715    tRRD = '10.0ns'
716
717    # Irrespective of size, tFAW is 50 ns
718    tXAW = '50ns'
719    activation_limit = 4
720
721    # Current values from datasheet
722    IDD0 = '8mA'
723    IDD02 = '60mA'
724    IDD2N = '0.8mA'
725    IDD2N2 = '26mA'
726    IDD3N = '2mA'
727    IDD3N2 = '34mA'
728    IDD4W = '2mA'
729    IDD4W2 = '190mA'
730    IDD4R = '2mA'
731    IDD4R2 = '230mA'
732    IDD5 = '28mA'
733    IDD52 = '150mA'
734    VDD = '1.8V'
735    VDD2 = '1.2V'
736