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/gem5/src/systemc/ext/channel/
H A D_using.hh12878:97fdce181f51 Wed Jun 13 21:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add some deprecated features to sc_clock.*.

Add in two deprecated typedefs, and a deprecated constructor. These
are necessary to get the regressions to build.

Change-Id: Id8320a67c680acbca0abaee9898158ffd2678d67
Reviewed-on: https://gem5-review.googlesource.com/11183
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dsc_clock.hh12878:97fdce181f51 Wed Jun 13 21:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add some deprecated features to sc_clock.*.

Add in two deprecated typedefs, and a deprecated constructor. These
are necessary to get the regressions to build.

Change-Id: Id8320a67c680acbca0abaee9898158ffd2678d67
Reviewed-on: https://gem5-review.googlesource.com/11183
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/generic/
H A Dlocked_mem.hh12218:8c5db15dc8e7 Tue Jun 13 06:14:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Signal the local monitor when clearing the global monitor

ARM systems require the coordination of the global and local
monitors. When the system is run without caches the global monitor is
implemented in the abstract memory object. This change adds a callback
from the abstract memory that notifies the local monitor when the
global monitor is cleared.

Additionally, for ARM systems the local monitor signals the event
register and wakes the thread context up. Subsequent wait-for-event
(WFE) instructions will be immediately signaled.

Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3760
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/power/insts/
H A Dmem.hh12385:288c62455dde Wed Dec 13 02:12:00 EST 2017 Gabe Black <gabeblack@google.com> cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

Neither of these were used, particularly memAccInst.

Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/o3/
H A Dimpl.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/cpu/testers/traffic_gen/
H A Ddram_gen.cc12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Dbase_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Ddram_rot_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Ddram_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Dlinear_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Drandom_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Didle_gen.hh12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/dev/alpha/
H A Dbackdoor.cc9808:13ffc0066b76 Thu Jul 11 22:57:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: make BasicPioDevice take size in constructor

Instead of relying on derived classes explicitly assigning
to the BasicPioDevice pioSize field, require them to pass
a size value in to the constructor.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
8931:7a1dfb191e3f Fri Apr 06 13:46:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
8789:a8b63a0ee14c Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in dev.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
H A DAlphaBackdoor.py8789:a8b63a0ee14c Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in dev.
/gem5/src/dev/arm/
H A Dvio_mmio.cc12740:beed0805c651 Mon Nov 07 13:21:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev-arm: Add a MMIO transport interface for VirtIO

The MMIO interface currently only supports a subset of version 0.9.5
of the VirtIO specification. It has the following known limitations:

* The queue size hint (the QUEUE_NUM register) is ignored.

* Queue alignment is assumed to be hard-coded to
VirtQueue::ALIGN_SIZE (4096 bytes).

* Only 4096 byte pages are currently supported.

Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/dev/ps2/
H A DSConscript12655:a1646f7c13ab Mon Apr 09 13:38:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9764
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/system/arm/dt/
H A Darmv8.dts12761:effd14bda656 Wed Jun 06 13:28:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
H A Darmv7.dts12761:effd14bda656 Wed Jun 06 13:28:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/configs/common/
H A D__init__.py11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages

This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
/gem5/src/arch/arm/linux/
H A Dlinux.hh11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power.
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.cc12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/sparc/
H A Disa.cc9425:a24092160ec7 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch: Move the ISA object to a separate section

After making the ISA an independent SimObject, it is serialized
automatically by the Python world. Previously, this just resulted in
an empty ISA section. This patch moves the contents of the ISA to that
section and removes the explicit ISA serialization from the thread
contexts, which makes it behave like a normal SimObject during
serialization.

Note: This patch breaks checkpoint backwards compatibility! Use the
cpt_upgrader.py utility to upgrade old checkpoints to the new format.
9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening.
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:

real 14m45.951s
user 13m57.528s
sys 0m3.452s

to:

real 12m19.777s
user 12m2.685s
sys 0m2.420s
/gem5/src/cpu/simple/
H A DAtomicSimpleCPU.py9647:5b6b315472e7 Mon Apr 22 13:20:00 EDT 2013 Dam Sunwoo <dam.sunwoo@arm.com> cpu: generate SimPoint basic block vector profiles

This patch is based on http://reviews.m5sim.org/r/1474/ originally written by
Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout
folder) based on start and end addresses of basic blocks.

Some comments to the original patch are addressed and hooks are added to create
and resume from checkpoints based on instruction counts dictated by external
SimPoint analysis tools.

SimPoint creation/resuming options will be implemented as a separate patch.
8839:eeb293859255 Mon Feb 13 06:43:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
5487:f0ac4112e128 Wed Jun 18 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> AtomicSimpleCPU: Separate data stalls from instruction stalls.
Separate simulation of icache stalls and dat stalls.
/gem5/src/dev/net/
H A Di8254xGBe.cc12963:214e39f63149 Mon Aug 13 02:23:00 EDT 2018 Pin-Yen Lin <treapking@google.com> net: Fix a bug when handling IPv6 packets

When gem5 runs with the networking support, it will run into an assertion
fail and aborted. This is because it tries to calculate checksum for IPv6
packet and this makes the IpPtr pointer ``ip'' become NULL. For that there
is functions and classes for IPv6 in base/inet.cc, I added IPv6 support for
i8254xGBe.cc. Because IPv6 header does not have identification number, I
ignored some of the debug messages using ip->id().

Change-Id: Ida5e36aefd2c5c26053f8152a0aac24191e7757c
Reviewed-on: https://gem5-review.googlesource.com/12339
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
11719:e832056deaed Tue Nov 29 13:04:00 EST 2016 Michael LeBeane <michael.lebeane@amd.com> dev: Fix buffer length when unserializing an eth pkt

Changeset 11701 only serialized the useful portion of of an ethernet packets'
payload. However, the device models expect each ethernet packet to contain
a 16KB buffer, even if there is no data in it. This patch adds a 'bufLength'
field to EthPacketData so the original size of the packet buffer can always
be unserialized.

Reported-by: Gabor Dozsa <Gabor.Dozsa@arm.com>
/gem5/tests/configs/
H A Dsimple-atomic-mp-ruby.py11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages

This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.
8839:eeb293859255 Mon Feb 13 06:43:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests.

Completed in 84 milliseconds

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