12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Nathan Binkert
292665SN/A *          Ali Saidi
302665SN/A *          Steve Reinhardt
312665SN/A *          Erik Hallnor
322SN/A */
332SN/A
341722SN/A/** @file
355480Snate@binkert.org * Alpha Console Backdoor Definition
362SN/A */
372SN/A
3811793Sbrandon.potter@amd.com#include "dev/alpha/backdoor.hh"
3911793Sbrandon.potter@amd.com
40146SN/A#include <cstddef>
412SN/A#include <string>
422SN/A
432158SN/A#include "arch/alpha/system.hh"
44146SN/A#include "base/inifile.hh"
451805SN/A#include "base/str.hh"
46146SN/A#include "base/trace.hh"
471717SN/A#include "cpu/base.hh"
482680SN/A#include "cpu/thread_context.hh"
498232Snate@binkert.org#include "debug/AlphaBackdoor.hh"
508741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh"
518741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh"
528741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh"
532521SN/A#include "dev/platform.hh"
5411264Sandreas.sandberg@arm.com#include "dev/storage/simple_disk.hh"
5512239Sandreas.sandberg@arm.com#include "dev/serial/terminal.hh"
563348SN/A#include "mem/packet.hh"
573348SN/A#include "mem/packet_access.hh"
582521SN/A#include "mem/physical.hh"
595480Snate@binkert.org#include "params/AlphaBackdoor.hh"
601805SN/A#include "sim/sim_object.hh"
612SN/A
622SN/Ausing namespace std;
632107SN/Ausing namespace AlphaISA;
642SN/A
655480Snate@binkert.orgAlphaBackdoor::AlphaBackdoor(const Params *p)
669808Sstever@gmail.com    : BasicPioDevice(p, sizeof(struct AlphaAccess)),
679808Sstever@gmail.com      disk(p->disk), terminal(p->terminal),
688806Sgblack@eecs.umich.edu      system(p->system), cpu(p->cpu)
692SN/A{
702521SN/A    alphaAccess = new Access();
712521SN/A    alphaAccess->last_offset = pioSize - 1;
722SN/A
732SN/A    alphaAccess->version = ALPHA_ACCESS_VERSION;
742SN/A    alphaAccess->diskUnit = 1;
75926SN/A
76926SN/A    alphaAccess->diskCount = 0;
77926SN/A    alphaAccess->diskPAddr = 0;
78926SN/A    alphaAccess->diskBlock = 0;
79926SN/A    alphaAccess->diskOperation = 0;
80926SN/A    alphaAccess->outputChar = 0;
81926SN/A    alphaAccess->inputChar = 0;
824395SN/A    std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
831805SN/A
842SN/A}
852SN/A
861634SN/Avoid
875480Snate@binkert.orgAlphaBackdoor::startup()
881634SN/A{
892549SN/A    system->setAlphaAccess(pioAddr);
905714Shsul@eecs.umich.edu    alphaAccess->numCPUs = system->numContexts();
911634SN/A    alphaAccess->kernStart = system->getKernelStart();
921634SN/A    alphaAccess->kernEnd = system->getKernelEnd();
931634SN/A    alphaAccess->entryPoint = system->getKernelEntry();
948931Sandreas.hansson@arm.com    alphaAccess->mem_size = system->memSize();
951634SN/A    alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
968741Sgblack@eecs.umich.edu    Tsunami *tsunami = dynamic_cast<Tsunami *>(params()->platform);
978806Sgblack@eecs.umich.edu    if (!tsunami)
988806Sgblack@eecs.umich.edu        fatal("Platform is not Tsunami.\n");
998741Sgblack@eecs.umich.edu    alphaAccess->intrClockFrequency = tsunami->io->frequency();
1001634SN/A}
1011634SN/A
1022512SN/ATick
1035480Snate@binkert.orgAlphaBackdoor::read(PacketPtr pkt)
1042SN/A{
1052SN/A
1062512SN/A    /** XXX Do we want to push the addr munging to a bus brige or something? So
1072512SN/A     * the device has it's physical address and then the bridge adds on whatever
1082512SN/A     * machine dependent address swizzle is required?
1092512SN/A     */
110540SN/A
1112641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
1122522SN/A
1132641SN/A    Addr daddr = pkt->getAddr() - pioAddr;
1142512SN/A
1154986SN/A    pkt->makeAtomicResponse();
1162521SN/A
1172641SN/A    switch (pkt->getSize())
118873SN/A    {
119873SN/A        case sizeof(uint32_t):
120873SN/A            switch (daddr)
121873SN/A            {
122873SN/A                case offsetof(AlphaAccess, last_offset):
12313232Sgabeblack@google.com                    pkt->setLE(alphaAccess->last_offset);
124873SN/A                    break;
125873SN/A                case offsetof(AlphaAccess, version):
12613232Sgabeblack@google.com                    pkt->setLE(alphaAccess->version);
127873SN/A                    break;
128873SN/A                case offsetof(AlphaAccess, numCPUs):
12913232Sgabeblack@google.com                    pkt->setLE(alphaAccess->numCPUs);
130873SN/A                    break;
131873SN/A                case offsetof(AlphaAccess, intrClockFrequency):
13213232Sgabeblack@google.com                    pkt->setLE(alphaAccess->intrClockFrequency);
133873SN/A                    break;
134873SN/A                default:
1352512SN/A                    /* Old console code read in everyting as a 32bit int
1362512SN/A                     * we now break that for better error checking.
1372512SN/A                     */
1384870SN/A                  pkt->setBadAddress();
139873SN/A            }
1405480Snate@binkert.org            DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
14113232Sgabeblack@google.com                    pkt->getLE<uint32_t>());
142873SN/A            break;
143873SN/A        case sizeof(uint64_t):
144873SN/A            switch (daddr)
145873SN/A            {
146873SN/A                case offsetof(AlphaAccess, inputChar):
14713232Sgabeblack@google.com                    pkt->setLE(terminal->console_in());
148873SN/A                    break;
149873SN/A                case offsetof(AlphaAccess, cpuClock):
15013232Sgabeblack@google.com                    pkt->setLE(alphaAccess->cpuClock);
151873SN/A                    break;
152873SN/A                case offsetof(AlphaAccess, mem_size):
15313232Sgabeblack@google.com                    pkt->setLE(alphaAccess->mem_size);
154873SN/A                    break;
155873SN/A                case offsetof(AlphaAccess, kernStart):
15613232Sgabeblack@google.com                    pkt->setLE(alphaAccess->kernStart);
157873SN/A                    break;
158873SN/A                case offsetof(AlphaAccess, kernEnd):
15913232Sgabeblack@google.com                    pkt->setLE(alphaAccess->kernEnd);
160873SN/A                    break;
161873SN/A                case offsetof(AlphaAccess, entryPoint):
16213232Sgabeblack@google.com                    pkt->setLE(alphaAccess->entryPoint);
163873SN/A                    break;
164873SN/A                case offsetof(AlphaAccess, diskUnit):
16513232Sgabeblack@google.com                    pkt->setLE(alphaAccess->diskUnit);
166873SN/A                    break;
167873SN/A                case offsetof(AlphaAccess, diskCount):
16813232Sgabeblack@google.com                    pkt->setLE(alphaAccess->diskCount);
169873SN/A                    break;
170873SN/A                case offsetof(AlphaAccess, diskPAddr):
17113232Sgabeblack@google.com                    pkt->setLE(alphaAccess->diskPAddr);
172873SN/A                    break;
173873SN/A                case offsetof(AlphaAccess, diskBlock):
17413232Sgabeblack@google.com                    pkt->setLE(alphaAccess->diskBlock);
175873SN/A                    break;
176873SN/A                case offsetof(AlphaAccess, diskOperation):
17713232Sgabeblack@google.com                    pkt->setLE(alphaAccess->diskOperation);
178873SN/A                    break;
179873SN/A                case offsetof(AlphaAccess, outputChar):
18013232Sgabeblack@google.com                    pkt->setLE(alphaAccess->outputChar);
181873SN/A                    break;
182873SN/A                default:
1832114SN/A                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
1842114SN/A                                 sizeof(alphaAccess->cpuStack[0]);
1852114SN/A
1862114SN/A                    if (cpunum >= 0 && cpunum < 64)
18713232Sgabeblack@google.com                        pkt->setLE(alphaAccess->cpuStack[cpunum]);
1882114SN/A                    else
1892114SN/A                        panic("Unknown 64bit access, %#x\n", daddr);
190873SN/A            }
1915480Snate@binkert.org            DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
19213232Sgabeblack@google.com                    pkt->getLE<uint64_t>());
193873SN/A            break;
194873SN/A        default:
1954870SN/A          pkt->setBadAddress();
1962SN/A    }
1972512SN/A    return pioDelay;
1982SN/A}
1992SN/A
2002512SN/ATick
2015480Snate@binkert.orgAlphaBackdoor::write(PacketPtr pkt)
2022SN/A{
2032641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
2042641SN/A    Addr daddr = pkt->getAddr() - pioAddr;
205430SN/A
20613232Sgabeblack@google.com    uint64_t val = pkt->getLE<uint64_t>();
2072641SN/A    assert(pkt->getSize() == sizeof(uint64_t));
2082SN/A
209430SN/A    switch (daddr) {
210430SN/A      case offsetof(AlphaAccess, diskUnit):
2112SN/A        alphaAccess->diskUnit = val;
212430SN/A        break;
2132SN/A
214430SN/A      case offsetof(AlphaAccess, diskCount):
2152SN/A        alphaAccess->diskCount = val;
216430SN/A        break;
2172SN/A
218430SN/A      case offsetof(AlphaAccess, diskPAddr):
2192SN/A        alphaAccess->diskPAddr = val;
220430SN/A        break;
2212SN/A
222430SN/A      case offsetof(AlphaAccess, diskBlock):
2232SN/A        alphaAccess->diskBlock = val;
224430SN/A        break;
2252SN/A
226430SN/A      case offsetof(AlphaAccess, diskOperation):
2272SN/A        if (val == 0x13)
2282SN/A            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
2292SN/A                       alphaAccess->diskCount);
2302SN/A        else
2312SN/A            panic("Invalid disk operation!");
2322SN/A
233430SN/A        break;
2342SN/A
235430SN/A      case offsetof(AlphaAccess, outputChar):
23612237Sandreas.sandberg@arm.com        terminal->writeData((char)(val & 0xff));
237430SN/A        break;
2382SN/A
239430SN/A      default:
2402114SN/A        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
2412114SN/A                     sizeof(alphaAccess->cpuStack[0]);
2427823Ssteve.reinhardt@amd.com        inform("Launching CPU %d @ %d", cpunum, curTick());
2432114SN/A        assert(val > 0 && "Must not access primary cpu");
2442114SN/A        if (cpunum >= 0 && cpunum < 64)
2452114SN/A            alphaAccess->cpuStack[cpunum] = val;
2462114SN/A        else
2472114SN/A            panic("Unknown 64bit access, %#x\n", daddr);
2482SN/A    }
2492SN/A
2504870SN/A    pkt->makeAtomicResponse();
2512SN/A
2522512SN/A    return pioDelay;
253545SN/A}
254545SN/A
2552SN/Avoid
25610905Sandreas.sandberg@arm.comAlphaBackdoor::Access::serialize(CheckpointOut &cp) const
2572SN/A{
258222SN/A    SERIALIZE_SCALAR(last_offset);
259222SN/A    SERIALIZE_SCALAR(version);
260222SN/A    SERIALIZE_SCALAR(numCPUs);
261222SN/A    SERIALIZE_SCALAR(mem_size);
262222SN/A    SERIALIZE_SCALAR(cpuClock);
263222SN/A    SERIALIZE_SCALAR(intrClockFrequency);
264222SN/A    SERIALIZE_SCALAR(kernStart);
265222SN/A    SERIALIZE_SCALAR(kernEnd);
266222SN/A    SERIALIZE_SCALAR(entryPoint);
267222SN/A    SERIALIZE_SCALAR(diskUnit);
268222SN/A    SERIALIZE_SCALAR(diskCount);
269222SN/A    SERIALIZE_SCALAR(diskPAddr);
270222SN/A    SERIALIZE_SCALAR(diskBlock);
271222SN/A    SERIALIZE_SCALAR(diskOperation);
272222SN/A    SERIALIZE_SCALAR(outputChar);
273430SN/A    SERIALIZE_SCALAR(inputChar);
2742114SN/A    SERIALIZE_ARRAY(cpuStack,64);
2752SN/A}
2762SN/A
2772SN/Avoid
27810905Sandreas.sandberg@arm.comAlphaBackdoor::Access::unserialize(CheckpointIn &cp)
2792SN/A{
280222SN/A    UNSERIALIZE_SCALAR(last_offset);
281222SN/A    UNSERIALIZE_SCALAR(version);
282222SN/A    UNSERIALIZE_SCALAR(numCPUs);
283222SN/A    UNSERIALIZE_SCALAR(mem_size);
284222SN/A    UNSERIALIZE_SCALAR(cpuClock);
285222SN/A    UNSERIALIZE_SCALAR(intrClockFrequency);
286222SN/A    UNSERIALIZE_SCALAR(kernStart);
287222SN/A    UNSERIALIZE_SCALAR(kernEnd);
288222SN/A    UNSERIALIZE_SCALAR(entryPoint);
289222SN/A    UNSERIALIZE_SCALAR(diskUnit);
290222SN/A    UNSERIALIZE_SCALAR(diskCount);
291222SN/A    UNSERIALIZE_SCALAR(diskPAddr);
292222SN/A    UNSERIALIZE_SCALAR(diskBlock);
293222SN/A    UNSERIALIZE_SCALAR(diskOperation);
294222SN/A    UNSERIALIZE_SCALAR(outputChar);
295430SN/A    UNSERIALIZE_SCALAR(inputChar);
2962114SN/A    UNSERIALIZE_ARRAY(cpuStack, 64);
297217SN/A}
2982SN/A
299217SN/Avoid
30010905Sandreas.sandberg@arm.comAlphaBackdoor::serialize(CheckpointOut &cp) const
301217SN/A{
30210905Sandreas.sandberg@arm.com    alphaAccess->serialize(cp);
303217SN/A}
304217SN/A
305217SN/Avoid
30610905Sandreas.sandberg@arm.comAlphaBackdoor::unserialize(CheckpointIn &cp)
307217SN/A{
30810905Sandreas.sandberg@arm.com    alphaAccess->unserialize(cp);
3092SN/A}
3102SN/A
3115480Snate@binkert.orgAlphaBackdoor *
3125480Snate@binkert.orgAlphaBackdoorParams::create()
3132SN/A{
3145480Snate@binkert.org    return new AlphaBackdoor(this);
3152SN/A}
316