#
13230:2988dc5d1d6f |
|
12-Oct-2018 |
Gabe Black <gabeblack@google.com> |
arm: Use little endian packet accessors.
We know data is little endian, so we can use those accessors explicitly.
Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12974:b840a646cfbd |
|
30-Aug-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Factory SimObject for generating ArmInterruptPin
With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation.
Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12740:beed0805c651 |
|
07-Nov-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev-arm: Add a MMIO transport interface for VirtIO
The MMIO interface currently only supports a subset of version 0.9.5 of the VirtIO specification. It has the following known limitations:
* The queue size hint (the QUEUE_NUM register) is ignored.
* Queue alignment is assumed to be hard-coded to VirtQueue::ALIGN_SIZE (4096 bytes).
* Only 4096 byte pages are currently supported.
Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2326 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|