13760SN/A/* 23760SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 33760SN/A * All rights reserved. 43760SN/A * 53760SN/A * Redistribution and use in source and binary forms, with or without 63760SN/A * modification, are permitted provided that the following conditions are 73760SN/A * met: redistributions of source code must retain the above copyright 83760SN/A * notice, this list of conditions and the following disclaimer; 93760SN/A * redistributions in binary form must reproduce the above copyright 103760SN/A * notice, this list of conditions and the following disclaimer in the 113760SN/A * documentation and/or other materials provided with the distribution; 123760SN/A * neither the name of the copyright holders nor the names of its 133760SN/A * contributors may be used to endorse or promote products derived from 143760SN/A * this software without specific prior written permission. 153760SN/A * 163760SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173760SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183760SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193760SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203760SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213760SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223760SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233760SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243760SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253760SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263760SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273760SN/A * 285597Sgblack@eecs.umich.edu * Authors: Kevin Lim 293760SN/A */ 303760SN/A 315597Sgblack@eecs.umich.edu#ifndef __CPU_O3_IMPL_HH__ 325597Sgblack@eecs.umich.edu#define __CPU_O3_IMPL_HH__ 333760SN/A 345597Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 363760SN/A#include "cpu/o3/cpu_policy.hh" 373760SN/A 383760SN/A// Forward declarations. 393760SN/Atemplate <class Impl> 405596SN/Aclass BaseO3DynInst; 413760SN/A 423760SN/Atemplate <class Impl> 435595SN/Aclass FullO3CPU; 443760SN/A 453760SN/A/** Implementation specific struct that defines several key types to the 463760SN/A * CPU, the stages within the CPU, the time buffers, and the DynInst. 473760SN/A * The struct defines the ISA, the CPU policy, the specific DynInst, the 483760SN/A * specific O3CPU, and all of the structs from the time buffers to do 493760SN/A * communication. 503760SN/A * This is one of the key things that must be defined for each hardware 513760SN/A * specific CPU implementation. 523760SN/A */ 535597Sgblack@eecs.umich.edustruct O3CPUImpl 543760SN/A{ 553760SN/A /** The type of MachInst. */ 563760SN/A typedef TheISA::MachInst MachInst; 573760SN/A 583760SN/A /** The CPU policy to be used, which defines all of the CPU stages. */ 595597Sgblack@eecs.umich.edu typedef SimpleCPUPolicy<O3CPUImpl> CPUPol; 603760SN/A 613760SN/A /** The DynInst type to be used. */ 625597Sgblack@eecs.umich.edu typedef BaseO3DynInst<O3CPUImpl> DynInst; 633760SN/A 643760SN/A /** The refcounted DynInst pointer to be used. In most cases this is 653760SN/A * what should be used, and not DynInst *. 663760SN/A */ 673760SN/A typedef RefCountingPtr<DynInst> DynInstPtr; 6813429Srekai.gonzalezalberquilla@arm.com typedef RefCountingPtr<const DynInst> DynInstConstPtr; 693760SN/A 703760SN/A /** The O3CPU type to be used. */ 715597Sgblack@eecs.umich.edu typedef FullO3CPU<O3CPUImpl> O3CPU; 723760SN/A 733760SN/A /** Same typedef, but for CPUType. BaseDynInst may not always use 743760SN/A * an O3 CPU, so it's clearer to call it CPUType instead in that 753760SN/A * case. 763760SN/A */ 773760SN/A typedef O3CPU CPUType; 783760SN/A 793760SN/A enum { 803760SN/A MaxWidth = 8, 813760SN/A MaxThreads = 4 823760SN/A }; 833760SN/A}; 843760SN/A 853760SN/A#endif // __CPU_O3_SPARC_IMPL_HH__ 86