111348Sandreas.sandberg@arm.com/* 211470Sandreas.sandberg@arm.com * Copyright (c) 2015-2016 ARM Limited 311348Sandreas.sandberg@arm.com * All rights reserved 411348Sandreas.sandberg@arm.com * 511348Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611348Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711348Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911348Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111348Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211348Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311348Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411348Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511348Sandreas.sandberg@arm.com * 1611348Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711348Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811348Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911348Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011348Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111348Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211348Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311348Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411348Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511348Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611348Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711348Sandreas.sandberg@arm.com * 2811348Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 2911348Sandreas.sandberg@arm.com */ 3011348Sandreas.sandberg@arm.com 3111348Sandreas.sandberg@arm.com/dts-v1/; 3211348Sandreas.sandberg@arm.com 3311348Sandreas.sandberg@arm.com#include CONF_PLATFORM 3411348Sandreas.sandberg@arm.com 3511348Sandreas.sandberg@arm.com#define CPU(n) \ 3611348Sandreas.sandberg@arm.com cpu@ ## n { \ 3711348Sandreas.sandberg@arm.com device_type = "cpu"; \ 3811348Sandreas.sandberg@arm.com compatible = "gem5,arm", "arm,cortex-a15"; \ 3911348Sandreas.sandberg@arm.com reg = < n >; \ 4011348Sandreas.sandberg@arm.com }; 4111348Sandreas.sandberg@arm.com 4211348Sandreas.sandberg@arm.com/ { 4311348Sandreas.sandberg@arm.com model = "V2P-CA15"; 4411348Sandreas.sandberg@arm.com compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 4511348Sandreas.sandberg@arm.com 4611348Sandreas.sandberg@arm.com memory@80000000 { 4711348Sandreas.sandberg@arm.com device_type = "memory"; 4811348Sandreas.sandberg@arm.com reg = <0 0x80000000 0x4 0x00000000>; 4911348Sandreas.sandberg@arm.com }; 5011348Sandreas.sandberg@arm.com 5111348Sandreas.sandberg@arm.com cpus { 5211348Sandreas.sandberg@arm.com #address-cells = <1>; 5311348Sandreas.sandberg@arm.com #size-cells = <0>; 5411348Sandreas.sandberg@arm.com 5511348Sandreas.sandberg@arm.com #if CONF_CPUS > 0 5611348Sandreas.sandberg@arm.com CPU(0) 5711348Sandreas.sandberg@arm.com #endif 5811348Sandreas.sandberg@arm.com #if CONF_CPUS > 1 5911348Sandreas.sandberg@arm.com CPU(1) 6011348Sandreas.sandberg@arm.com #endif 6111348Sandreas.sandberg@arm.com #if CONF_CPUS > 2 6211348Sandreas.sandberg@arm.com CPU(2) 6311348Sandreas.sandberg@arm.com #endif 6411348Sandreas.sandberg@arm.com #if CONF_CPUS > 3 6511348Sandreas.sandberg@arm.com CPU(3) 6611348Sandreas.sandberg@arm.com #endif 6711348Sandreas.sandberg@arm.com #if CONF_CPUS > 4 6811348Sandreas.sandberg@arm.com CPU(4) 6911348Sandreas.sandberg@arm.com #endif 7011348Sandreas.sandberg@arm.com #if CONF_CPUS > 5 7111348Sandreas.sandberg@arm.com CPU(5) 7211348Sandreas.sandberg@arm.com #endif 7311348Sandreas.sandberg@arm.com #if CONF_CPUS > 6 7411348Sandreas.sandberg@arm.com CPU(6) 7511348Sandreas.sandberg@arm.com #endif 7611348Sandreas.sandberg@arm.com #if CONF_CPUS > 7 7711348Sandreas.sandberg@arm.com CPU(7) 7811348Sandreas.sandberg@arm.com #endif 7911348Sandreas.sandberg@arm.com #if CONF_CPUS > 8 8011348Sandreas.sandberg@arm.com CPU(8) 8111348Sandreas.sandberg@arm.com #endif 8211348Sandreas.sandberg@arm.com #if CONF_CPUS > 9 8311348Sandreas.sandberg@arm.com CPU(9) 8411348Sandreas.sandberg@arm.com #endif 8511348Sandreas.sandberg@arm.com #if CONF_CPUS > 10 8611348Sandreas.sandberg@arm.com CPU(10) 8711348Sandreas.sandberg@arm.com #endif 8811348Sandreas.sandberg@arm.com #if CONF_CPUS > 11 8911348Sandreas.sandberg@arm.com CPU(11) 9011348Sandreas.sandberg@arm.com #endif 9111348Sandreas.sandberg@arm.com #if CONF_CPUS > 12 9211348Sandreas.sandberg@arm.com CPU(12) 9311348Sandreas.sandberg@arm.com #endif 9411348Sandreas.sandberg@arm.com #if CONF_CPUS > 13 9511348Sandreas.sandberg@arm.com CPU(13) 9611348Sandreas.sandberg@arm.com #endif 9711348Sandreas.sandberg@arm.com #if CONF_CPUS > 14 9811348Sandreas.sandberg@arm.com CPU(14) 9911348Sandreas.sandberg@arm.com #endif 10011348Sandreas.sandberg@arm.com #if CONF_CPUS > 15 10111348Sandreas.sandberg@arm.com CPU(15) 10211348Sandreas.sandberg@arm.com #endif 10311348Sandreas.sandberg@arm.com #if CONF_CPUS > 16 10411348Sandreas.sandberg@arm.com #error Unsupported number of CPUs 10511348Sandreas.sandberg@arm.com #endif 10611348Sandreas.sandberg@arm.com }; 10711348Sandreas.sandberg@arm.com 10811348Sandreas.sandberg@arm.com virt-encoder { 10911470Sandreas.sandberg@arm.com compatible = "drm,virtual-encoder"; 11011348Sandreas.sandberg@arm.com port { 11112761Sandreas.sandberg@arm.com dp0_virt_input: endpoint@0 { 11212761Sandreas.sandberg@arm.com remote-endpoint = <&dp0_output>; 11311348Sandreas.sandberg@arm.com }; 11411348Sandreas.sandberg@arm.com }; 11511348Sandreas.sandberg@arm.com 11611348Sandreas.sandberg@arm.com display-timings { 11711348Sandreas.sandberg@arm.com native-mode = <&timing0>; 11811348Sandreas.sandberg@arm.com 11911348Sandreas.sandberg@arm.com timing0: timing_1080p60 { 12011348Sandreas.sandberg@arm.com /* 1920x1080-60 */ 12111348Sandreas.sandberg@arm.com clock-frequency = <148500000>; 12211348Sandreas.sandberg@arm.com hactive = <1920>; 12311348Sandreas.sandberg@arm.com vactive = <1080>; 12411348Sandreas.sandberg@arm.com hfront-porch = <148>; 12511348Sandreas.sandberg@arm.com hback-porch = <88>; 12611348Sandreas.sandberg@arm.com hsync-len = <44>; 12711348Sandreas.sandberg@arm.com vfront-porch = <36>; 12811348Sandreas.sandberg@arm.com vback-porch = <4>; 12911348Sandreas.sandberg@arm.com vsync-len = <5>; 13011348Sandreas.sandberg@arm.com }; 13111348Sandreas.sandberg@arm.com }; 13211348Sandreas.sandberg@arm.com }; 13311348Sandreas.sandberg@arm.com}; 13411348Sandreas.sandberg@arm.com 13512761Sandreas.sandberg@arm.com&dp0 { 13611348Sandreas.sandberg@arm.com status = "ok"; 13711348Sandreas.sandberg@arm.com 13811348Sandreas.sandberg@arm.com port { 13912761Sandreas.sandberg@arm.com dp0_output: endpoint@0 { 14012761Sandreas.sandberg@arm.com remote-endpoint = <&dp0_virt_input>; 14111348Sandreas.sandberg@arm.com }; 14211348Sandreas.sandberg@arm.com }; 14311348Sandreas.sandberg@arm.com}; 144