| /gem5/ext/sst/ |
| H A D | ExtMaster.hh | 78 const ExternalMaster& port; member in class:SST::gem5::ExtMaster
|
| H A D | ExtSlave.cc | 55 ExtSlave(gem5Component *g5c, Output &out, ::ExternalSlave& port, std::string &name) argument
|
| /gem5/src/dev/net/ |
| H A D | tcp_iface.cc | 115 TCPIface::listen(int port) argument
|
| /gem5/src/sim/ |
| H A D | debug.cc | 137 setRemoteGDBPort(int port) argument
|
| H A D | port.hh | 151 operator <<(std::ostream &os, const Port &port) argument
[all...] |
| H A D | system.cc | 265 int port = getRemoteGDBPort(); local
|
| /gem5/util/tlm/src/ |
| H A D | sc_peq.hh | 55 OWNER& port; member in class:Gem5SystemC::PayloadEvent
|
| H A D | sim_control.cc | 181 Gem5SimControl::registerSlavePort(const std::string& name, SCSlavePort* port) argument
192 Gem5SimControl::registerMasterPort(const std::string& name, SCMasterPort* port) argument
|
| /gem5/src/systemc/core/ |
| H A D | sc_spawn.cc | 179 sc_spawn_options::reset_signal_is(const sc_in<bool> &port, bool value) argument
185 sc_spawn_options::reset_signal_is(const sc_inout<bool> &port, bool value) argument
191 sc_spawn_options::reset_signal_is(const sc_out<bool> &port, bool value) argument
205 sc_spawn_options::async_reset_signal_is(const sc_in<bool> &port, bool value) argument
211 sc_spawn_options::async_reset_signal_is(const sc_inout<bool> &port, bool value) argument
217 async_reset_signal_is(const sc_out<bool> &port, bool value) argument
[all...] |
| H A D | module.cc | 118 auto port = *portIt; local
|
| H A D | sensitivity.cc | 143 Port *port = Port::fromPort(pb); local
160 Port *port = Port::fromPort(f->port()); local
|
| /gem5/src/mem/ |
| H A D | dramsim2.hh | 89 MemoryPort port; member in class:DRAMSim2
|
| H A D | simple_mem.hh | 103 MemoryPort port; member in class:SimpleMemory
|
| H A D | port_proxy.hh | 105 PortProxy(const MasterPort &port, unsigned int cacheLineSize) : argument
[all...] |
| /gem5/src/arch/arm/ |
| H A D | ArmTLB.py | 59 port = MasterPort("Port used by the two table walkers") variable in class:ArmTableWalker
|
| H A D | stage2_mmu.hh | 62 DmaPort port; member in class:ArmISA::Stage2MMU
|
| /gem5/src/systemc/tlm_bridge/ |
| H A D | sc_peq.hh | 55 OWNER& port; member in class:Gem5SystemC::PayloadEvent
|
| /gem5/src/arch/x86/ |
| H A D | x86_traits.hh | 81 x86IOAddress(const uint32_t port) argument
|
| /gem5/src/systemc/tests/systemc/communication/ports/test01/ |
| H A D | test01.cpp | 51 sc_port<sc_signal_in_if<float> > port; local
|
| /gem5/src/systemc/tests/systemc/compliance_1666/test200/ |
| H A D | test200.cpp | 36 Port port;
local
|
| /gem5/src/mem/qos/ |
| H A D | mem_sink.hh | 164 MemoryPort port; member in class:QoS::MemSinkCtrl
|
| /gem5/src/cpu/testers/rubytest/ |
| H A D | RubyTester.cc | 88 CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i), local
95 CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), local
[all...] |
| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | BaseTrafficGen.py | 64 port = MasterPort("Master port") variable in class:BaseTrafficGen
|
| /gem5/src/gpu-compute/ |
| H A D | X86GPUTLB.py | 45 port = SlavePort("Port for the hardware table walker") variable in class:X86PagetableWalker
|
| /gem5/util/term/ |
| H A D | term.c | 62 char *host, *port, *endp; local
112 remote_connect(char *host, char *port, struct addrinfo hints) argument
|