16899SN/A/*
29542Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited
38851Sandreas.hansson@arm.com * All rights reserved
48851Sandreas.hansson@arm.com *
58851Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68851Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78851Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88851Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98851Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108851Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118851Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128851Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138851Sandreas.hansson@arm.com *
146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc.
166899SN/A * All rights reserved.
176899SN/A *
186899SN/A * Redistribution and use in source and binary forms, with or without
196899SN/A * modification, are permitted provided that the following conditions are
206899SN/A * met: redistributions of source code must retain the above copyright
216899SN/A * notice, this list of conditions and the following disclaimer;
226899SN/A * redistributions in binary form must reproduce the above copyright
236899SN/A * notice, this list of conditions and the following disclaimer in the
246899SN/A * documentation and/or other materials provided with the distribution;
256899SN/A * neither the name of the copyright holders nor the names of its
266899SN/A * contributors may be used to endorse or promote products derived from
276899SN/A * this software without specific prior written permission.
286899SN/A *
296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406899SN/A */
416899SN/A
4211793Sbrandon.potter@amd.com#include "cpu/testers/rubytest/RubyTester.hh"
4311793Sbrandon.potter@amd.com
4412334Sgabeblack@google.com#include "base/logging.hh"
4511800Sbrandon.potter@amd.com#include "base/trace.hh"
467632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh"
478232Snate@binkert.org#include "debug/RubyTest.hh"
487053SN/A#include "mem/ruby/common/SubBlock.hh"
496899SN/A#include "sim/sim_exit.hh"
508832SAli.Saidi@ARM.com#include "sim/system.hh"
516899SN/A
526899SN/ARubyTester::RubyTester(const Params *p)
5313892Sgabeblack@google.com  : ClockedObject(p),
5412129Sspwilson2@wisc.edu    checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
5512129Sspwilson2@wisc.edu                    false, Event::CPU_Tick_Pri),
5612680Sgiacomo.travaglini@arm.com    _masterId(p->system->getMasterId(this)),
5710412Sandreas.hansson@arm.com    m_checkTable_ptr(nullptr),
588932SBrad.Beckmann@amd.com    m_num_cpus(p->num_cpus),
596899SN/A    m_checks_to_complete(p->checks_to_complete),
606899SN/A    m_deadlock_threshold(p->deadlock_threshold),
6110412Sandreas.hansson@arm.com    m_num_writers(0),
6210412Sandreas.hansson@arm.com    m_num_readers(0),
638184Ssomayeh@cs.wisc.edu    m_wakeup_frequency(p->wakeup_frequency),
648932SBrad.Beckmann@amd.com    m_check_flush(p->check_flush),
6511266SBrad.Beckmann@amd.com    m_num_inst_only_ports(p->port_cpuInstPort_connection_count),
6611266SBrad.Beckmann@amd.com    m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count)
676899SN/A{
687053SN/A    m_checks_completed = 0;
696899SN/A
708932SBrad.Beckmann@amd.com    //
718932SBrad.Beckmann@amd.com    // Create the requested inst and data ports and place them on the
728932SBrad.Beckmann@amd.com    // appropriate read and write port lists.  The reason for the subtle
738932SBrad.Beckmann@amd.com    // difference between inst and data ports vs. read and write ports is
748932SBrad.Beckmann@amd.com    // from the tester's perspective, it only needs to know whether a port
758932SBrad.Beckmann@amd.com    // supports reads (checks) or writes (actions).  Meanwhile, the protocol
768932SBrad.Beckmann@amd.com    // controllers have data ports (support read and writes) or inst ports
778932SBrad.Beckmann@amd.com    // (support only reads).
788932SBrad.Beckmann@amd.com    // Note: the inst ports are the lowest elements of the readPort vector,
798932SBrad.Beckmann@amd.com    // then the data ports are added to the readPort vector
808932SBrad.Beckmann@amd.com    //
8111266SBrad.Beckmann@amd.com    int idx = 0;
828932SBrad.Beckmann@amd.com    for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
838932SBrad.Beckmann@amd.com        readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
8411266SBrad.Beckmann@amd.com                                        this, i, idx));
8511266SBrad.Beckmann@amd.com        idx++;
8611266SBrad.Beckmann@amd.com    }
8711266SBrad.Beckmann@amd.com    for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) {
8811266SBrad.Beckmann@amd.com        CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i),
8911266SBrad.Beckmann@amd.com                                    this, i, idx);
9011266SBrad.Beckmann@amd.com        readPorts.push_back(port);
9111266SBrad.Beckmann@amd.com        writePorts.push_back(port);
9211266SBrad.Beckmann@amd.com        idx++;
938932SBrad.Beckmann@amd.com    }
948932SBrad.Beckmann@amd.com    for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
958950Sandreas.hansson@arm.com        CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
9611266SBrad.Beckmann@amd.com                                    this, i, idx);
978932SBrad.Beckmann@amd.com        readPorts.push_back(port);
988932SBrad.Beckmann@amd.com        writePorts.push_back(port);
9911266SBrad.Beckmann@amd.com        idx++;
1008851Sandreas.hansson@arm.com    }
1018851Sandreas.hansson@arm.com
1027053SN/A    // add the check start event to the event queue
1037053SN/A    schedule(checkStartEvent, 1);
1046899SN/A}
1056899SN/A
1066899SN/ARubyTester::~RubyTester()
1076899SN/A{
1087053SN/A    delete m_checkTable_ptr;
1098932SBrad.Beckmann@amd.com    // Only delete the readPorts since the writePorts are just a subset
1108932SBrad.Beckmann@amd.com    for (int i = 0; i < readPorts.size(); i++)
1118932SBrad.Beckmann@amd.com        delete readPorts[i];
1126899SN/A}
1136899SN/A
1147053SN/Avoid
1157053SN/ARubyTester::init()
1166899SN/A{
1178932SBrad.Beckmann@amd.com    assert(writePorts.size() > 0 && readPorts.size() > 0);
1186899SN/A
1198932SBrad.Beckmann@amd.com    m_last_progress_vector.resize(m_num_cpus);
1207053SN/A    for (int i = 0; i < m_last_progress_vector.size(); i++) {
12110302Snilay@cs.wisc.edu        m_last_progress_vector[i] = Cycles(0);
1227053SN/A    }
1236899SN/A
1248932SBrad.Beckmann@amd.com    m_num_writers = writePorts.size();
1258932SBrad.Beckmann@amd.com    m_num_readers = readPorts.size();
12611266SBrad.Beckmann@amd.com    assert(m_num_readers == m_num_cpus);
1276899SN/A
1288932SBrad.Beckmann@amd.com    m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
1296899SN/A}
1306899SN/A
13113784Sgabeblack@google.comPort &
13213784Sgabeblack@google.comRubyTester::getPort(const std::string &if_name, PortID idx)
1336899SN/A{
13411266SBrad.Beckmann@amd.com    if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
13511266SBrad.Beckmann@amd.com        if_name != "cpuDataPort") {
1368922Swilliam.wang@arm.com        // pass it along to our super class
13713892Sgabeblack@google.com        return ClockedObject::getPort(if_name, idx);
1388922Swilliam.wang@arm.com    } else {
1398932SBrad.Beckmann@amd.com        if (if_name == "cpuInstPort") {
14011266SBrad.Beckmann@amd.com            if (idx > m_num_inst_only_ports) {
14113784Sgabeblack@google.com                panic("RubyTester::getPort: unknown inst port %d\n",
1428932SBrad.Beckmann@amd.com                      idx);
1438932SBrad.Beckmann@amd.com            }
1448932SBrad.Beckmann@amd.com            //
14511266SBrad.Beckmann@amd.com            // inst ports map to the lowest readPort elements
1468932SBrad.Beckmann@amd.com            //
1478932SBrad.Beckmann@amd.com            return *readPorts[idx];
14811266SBrad.Beckmann@amd.com        } else if (if_name == "cpuInstDataPort") {
14911266SBrad.Beckmann@amd.com            if (idx > m_num_inst_data_ports) {
15013784Sgabeblack@google.com                panic("RubyTester::getPort: unknown inst+data port %d\n",
15111266SBrad.Beckmann@amd.com                      idx);
15211266SBrad.Beckmann@amd.com            }
15311266SBrad.Beckmann@amd.com            int read_idx = idx + m_num_inst_only_ports;
15411266SBrad.Beckmann@amd.com            //
15511266SBrad.Beckmann@amd.com            // inst+data ports map to the next readPort elements
15611266SBrad.Beckmann@amd.com            //
15711266SBrad.Beckmann@amd.com            return *readPorts[read_idx];
1588932SBrad.Beckmann@amd.com        } else {
1598932SBrad.Beckmann@amd.com            assert(if_name == "cpuDataPort");
1608932SBrad.Beckmann@amd.com            //
16111266SBrad.Beckmann@amd.com            // data only ports map to the final readPort elements
1628932SBrad.Beckmann@amd.com            //
16311266SBrad.Beckmann@amd.com            if (idx > (static_cast<int>(readPorts.size()) -
16411266SBrad.Beckmann@amd.com                       (m_num_inst_only_ports + m_num_inst_data_ports))) {
16513784Sgabeblack@google.com                panic("RubyTester::getPort: unknown data port %d\n",
1668932SBrad.Beckmann@amd.com                      idx);
1678932SBrad.Beckmann@amd.com            }
16811266SBrad.Beckmann@amd.com            int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports;
1698932SBrad.Beckmann@amd.com            return *readPorts[read_idx];
1708922Swilliam.wang@arm.com        }
17111266SBrad.Beckmann@amd.com        // Note: currently the Ruby Tester does not support write only ports
17211266SBrad.Beckmann@amd.com        // but that could easily be added here
1736899SN/A    }
1746899SN/A}
1756899SN/A
1766899SN/Abool
1778975Sandreas.hansson@arm.comRubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
1786899SN/A{
1797053SN/A    // retrieve the subblock and call hitCallback
1807053SN/A    RubyTester::SenderState* senderState =
1817053SN/A        safe_cast<RubyTester::SenderState*>(pkt->senderState);
1829542Sandreas.hansson@arm.com    SubBlock& subblock = senderState->subBlock;
1836899SN/A
18411266SBrad.Beckmann@amd.com    tester->hitCallback(globalIdx, &subblock);
1857053SN/A
1867053SN/A    // Now that the tester has completed, delete the senderState
1877053SN/A    // (includes sublock) and the packet, then return
1889542Sandreas.hansson@arm.com    delete pkt->senderState;
1897053SN/A    delete pkt;
1907053SN/A    return true;
1916899SN/A}
1926899SN/A
1938950Sandreas.hansson@arm.combool
19411266SBrad.Beckmann@amd.comRubyTester::isInstOnlyCpuPort(int idx)
1958950Sandreas.hansson@arm.com{
19611266SBrad.Beckmann@amd.com    return idx < m_num_inst_only_ports;
19711266SBrad.Beckmann@amd.com}
19811266SBrad.Beckmann@amd.com
19911266SBrad.Beckmann@amd.combool
20011266SBrad.Beckmann@amd.comRubyTester::isInstDataCpuPort(int idx)
20111266SBrad.Beckmann@amd.com{
20211266SBrad.Beckmann@amd.com    return ((idx >= m_num_inst_only_ports) &&
20311266SBrad.Beckmann@amd.com            (idx < (m_num_inst_only_ports + m_num_inst_data_ports)));
2048950Sandreas.hansson@arm.com}
2058950Sandreas.hansson@arm.com
2068922Swilliam.wang@arm.comMasterPort*
2078932SBrad.Beckmann@amd.comRubyTester::getReadableCpuPort(int idx)
2086899SN/A{
2098932SBrad.Beckmann@amd.com    assert(idx >= 0 && idx < readPorts.size());
2106899SN/A
2118932SBrad.Beckmann@amd.com    return readPorts[idx];
2128932SBrad.Beckmann@amd.com}
2138932SBrad.Beckmann@amd.com
2148932SBrad.Beckmann@amd.comMasterPort*
2158932SBrad.Beckmann@amd.comRubyTester::getWritableCpuPort(int idx)
2168932SBrad.Beckmann@amd.com{
2178932SBrad.Beckmann@amd.com    assert(idx >= 0 && idx < writePorts.size());
2188932SBrad.Beckmann@amd.com
2198932SBrad.Beckmann@amd.com    return writePorts[idx];
2206899SN/A}
2216899SN/A
2227053SN/Avoid
2237053SN/ARubyTester::hitCallback(NodeID proc, SubBlock* data)
2246899SN/A{
2257053SN/A    // Mark that we made progress
2269475Snilay@cs.wisc.edu    m_last_progress_vector[proc] = curCycle();
2276899SN/A
22811266SBrad.Beckmann@amd.com    DPRINTF(RubyTest, "completed request for proc: %d", proc);
22911266SBrad.Beckmann@amd.com    DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ",
2307053SN/A            data->getAddress(), data->getSize());
2317053SN/A    for (int byte = 0; byte < data->getSize(); byte++) {
23211266SBrad.Beckmann@amd.com        DPRINTFR(RubyTest, "%d ", data->getByte(byte));
2337053SN/A    }
23411266SBrad.Beckmann@amd.com    DPRINTFR(RubyTest, "\n");
2356899SN/A
2367053SN/A    // This tells us our store has 'completed' or for a load gives us
2377053SN/A    // back the data to make the check
2387053SN/A    Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
2397053SN/A    assert(check_ptr != NULL);
2409475Snilay@cs.wisc.edu    check_ptr->performCallback(proc, data, curCycle());
2416899SN/A}
2426899SN/A
2437053SN/Avoid
2447053SN/ARubyTester::wakeup()
2457053SN/A{
2467053SN/A    if (m_checks_completed < m_checks_to_complete) {
2477053SN/A        // Try to perform an action or check
2487053SN/A        Check* check_ptr = m_checkTable_ptr->getRandomCheck();
2497053SN/A        assert(check_ptr != NULL);
2507053SN/A        check_ptr->initiate();
2517053SN/A
2527053SN/A        checkForDeadlock();
2537053SN/A
2547823Ssteve.reinhardt@amd.com        schedule(checkStartEvent, curTick() + m_wakeup_frequency);
2557053SN/A    } else {
2567053SN/A        exitSimLoop("Ruby Tester completed");
2577053SN/A    }
2586899SN/A}
2596899SN/A
2607053SN/Avoid
2617053SN/ARubyTester::checkForDeadlock()
2626899SN/A{
2637053SN/A    int size = m_last_progress_vector.size();
26410302Snilay@cs.wisc.edu    Cycles current_time = curCycle();
2657053SN/A    for (int processor = 0; processor < size; processor++) {
2667053SN/A        if ((current_time - m_last_progress_vector[processor]) >
2677053SN/A                m_deadlock_threshold) {
2687805Snilay@cs.wisc.edu            panic("Deadlock detected: current_time: %d last_progress_time: %d "
2697805Snilay@cs.wisc.edu                  "difference:  %d processor: %d\n",
2707805Snilay@cs.wisc.edu                  current_time, m_last_progress_vector[processor],
2717805Snilay@cs.wisc.edu                  current_time - m_last_progress_vector[processor], processor);
2727053SN/A        }
2736899SN/A    }
2746899SN/A}
2756899SN/A
2767053SN/Avoid
2777055SN/ARubyTester::print(std::ostream& out) const
2786899SN/A{
2797055SN/A    out << "[RubyTester]" << std::endl;
2806899SN/A}
2816899SN/A
2826899SN/ARubyTester *
2836899SN/ARubyTesterParams::create()
2846899SN/A{
2856899SN/A    return new RubyTester(this);
2866899SN/A}
287