1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __MEM_SIMPLE_MEMORY_HH__
50#define __MEM_SIMPLE_MEMORY_HH__
51
52#include <list>
53
54#include "mem/abstract_mem.hh"
55#include "mem/port.hh"
56#include "params/SimpleMemory.hh"
57
58/**
59 * The simple memory is a basic single-ported memory controller with
60 * a configurable throughput and latency.
61 *
62 * @sa  \ref gem5MemorySystem "gem5 Memory System"
63 */
64class SimpleMemory : public AbstractMemory
65{
66
67  private:
68
69    /**
70     * A deferred packet stores a packet along with its scheduled
71     * transmission time
72     */
73    class DeferredPacket
74    {
75
76      public:
77
78        const Tick tick;
79        const PacketPtr pkt;
80
81        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
82        { }
83    };
84
85    class MemoryPort : public SlavePort
86    {
87      private:
88        SimpleMemory& memory;
89
90      public:
91        MemoryPort(const std::string& _name, SimpleMemory& _memory);
92
93      protected:
94        Tick recvAtomic(PacketPtr pkt) override;
95        Tick recvAtomicBackdoor(
96                PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
97        void recvFunctional(PacketPtr pkt) override;
98        bool recvTimingReq(PacketPtr pkt) override;
99        void recvRespRetry() override;
100        AddrRangeList getAddrRanges() const override;
101    };
102
103    MemoryPort port;
104
105    /**
106     * Latency from that a request is accepted until the response is
107     * ready to be sent.
108     */
109    const Tick latency;
110
111    /**
112     * Fudge factor added to the latency.
113     */
114    const Tick latency_var;
115
116    /**
117     * Internal (unbounded) storage to mimic the delay caused by the
118     * actual memory access. Note that this is where the packet spends
119     * the memory latency.
120     */
121    std::list<DeferredPacket> packetQueue;
122
123    /**
124     * Bandwidth in ticks per byte. The regulation affects the
125     * acceptance rate of requests and the queueing takes place after
126     * the regulation.
127     */
128    const double bandwidth;
129
130    /**
131     * Track the state of the memory as either idle or busy, no need
132     * for an enum with only two states.
133     */
134    bool isBusy;
135
136    /**
137     * Remember if we have to retry an outstanding request that
138     * arrived while we were busy.
139     */
140    bool retryReq;
141
142    /**
143     * Remember if we failed to send a response and are awaiting a
144     * retry. This is only used as a check.
145     */
146    bool retryResp;
147
148    /**
149     * Release the memory after being busy and send a retry if a
150     * request was rejected in the meanwhile.
151     */
152    void release();
153
154    EventFunctionWrapper releaseEvent;
155
156    /**
157     * Dequeue a packet from our internal packet queue and move it to
158     * the port where it will be sent as soon as possible.
159     */
160    void dequeue();
161
162    EventFunctionWrapper dequeueEvent;
163
164    /**
165     * Detemine the latency.
166     *
167     * @return the latency seen by the current packet
168     */
169    Tick getLatency() const;
170
171    /**
172     * Upstream caches need this packet until true is returned, so
173     * hold it for deletion until a subsequent call
174     */
175    std::unique_ptr<Packet> pendingDelete;
176
177  public:
178
179    SimpleMemory(const SimpleMemoryParams *p);
180
181    DrainState drain() override;
182
183    Port &getPort(const std::string &if_name,
184                  PortID idx=InvalidPortID) override;
185    void init() override;
186
187  protected:
188    Tick recvAtomic(PacketPtr pkt);
189    Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
190    void recvFunctional(PacketPtr pkt);
191    bool recvTimingReq(PacketPtr pkt);
192    void recvRespRetry();
193};
194
195#endif //__MEM_SIMPLE_MEMORY_HH__
196