xref: /gem5/ext/sst/ExtMaster.hh

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// Copyright 2009-2014 Sandia Coporation.  Under the terms
// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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#ifndef EXT_SST_EXTMASTER_HH
#define EXT_SST_EXTMASTER_HH

#include <list>
#include <set>

#include <core/component.h>
#include <elements/memHierarchy/memEvent.h>

#include <sim/sim_object.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
#include <mem/external_master.hh>

namespace SST {

using MemHierarchy::MemEvent;
class Link;
class Event;

namespace MemHierarchy {
class MemNIC;
}

namespace gem5 {

class gem5Component;

class ExtMaster : public ExternalMaster::Port {

    enum Phase { CONSTRUCTION, INIT, RUN };

    Output& out;
    const ExternalMaster& port;
    Phase simPhase;

    gem5Component *const gem5;
    const std::string name;
    std::list<PacketPtr> sendQ;
    bool blocked() { return !sendQ.empty(); }

    MemHierarchy::MemNIC * nic;

    struct SenderState : public Packet::SenderState
    {
        MemEvent *event;
        SenderState(MemEvent* e) : event(e) {}
    };

    std::set<AddrRange> ranges;

public:
    bool recvTimingResp(PacketPtr);
    void recvReqRetry();

    ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
    void init(unsigned phase);
    void setup();
    void finish();

    void clock();

    // receive Requests from SST bound for a gem5 slave;
    // this module is "external" from gem5's perspective, thus ExternalMaster.
    void handleEvent(SST::Event*);

protected:
    virtual void recvRangeChange();
};

} // namespace gem5
} // namespace SST

#endif