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36// Copyright 2009-2014 Sandia Coporation.  Under the terms
37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
38// Government retains certain rights in this software.
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40// Copyright (c) 2009-2014, Sandia Corporation
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42//
43// For license information, see the LICENSE file in the current directory.
44
45#ifndef EXT_SST_EXTMASTER_HH
46#define EXT_SST_EXTMASTER_HH
47
48#include <list>
49#include <set>
50
51#include <core/component.h>
52#include <elements/memHierarchy/memEvent.h>
53
54#include <sim/sim_object.hh>
55#include <mem/packet.hh>
56#include <mem/request.hh>
57#include <mem/external_master.hh>
58
59namespace SST {
60
61using MemHierarchy::MemEvent;
62class Link;
63class Event;
64
65namespace MemHierarchy {
66class MemNIC;
67}
68
69namespace gem5 {
70
71class gem5Component;
72
73class ExtMaster : public ExternalMaster::Port {
74
75    enum Phase { CONSTRUCTION, INIT, RUN };
76
77    Output& out;
78    const ExternalMaster& port;
79    Phase simPhase;
80
81    gem5Component *const gem5;
82    const std::string name;
83    std::list<PacketPtr> sendQ;
84    bool blocked() { return !sendQ.empty(); }
85
86    MemHierarchy::MemNIC * nic;
87
88    struct SenderState : public Packet::SenderState
89    {
90        MemEvent *event;
91        SenderState(MemEvent* e) : event(e) {}
92    };
93
94    std::set<AddrRange> ranges;
95
96public:
97    bool recvTimingResp(PacketPtr);
98    void recvReqRetry();
99
100    ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
101    void init(unsigned phase);
102    void setup();
103    void finish();
104
105    void clock();
106
107    // receive Requests from SST bound for a gem5 slave;
108    // this module is "external" from gem5's perspective, thus ExternalMaster.
109    void handleEvent(SST::Event*);
110
111protected:
112    virtual void recvRangeChange();
113};
114
115} // namespace gem5
116} // namespace SST
117
118#endif
119