arch/x86: add support for explicit CC register file

Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.

Nilay Vaish also contributed to this patch.

x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since it
is not being used any where in the implementation, it creates an unnecessary
dependency. Hence, it is being moved to a separate register.

ISA: Back-out NoopMachInst as a StaticInstPtr change.

ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.

X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.

copyright: Change HP copyright on x86 code to be more friendly

X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.

includes: sort includes again

types: Move stuff for global types into src/base/types.hh

X86: Fix the ordering of special physical address ranges.

X86: Make APICs communicate through the memory system.

X86: Make the local APIC accessible through the memory system directly, and make the timer work.

X86: Start implementing the south bridge stuff.

X86: Get PCI config space to work, and adjust address space prefix numbering scheme.

X86: Make the IO ports work using extra physical address lines. Add a serial port.

X86: Implement the in/out instructions. These will still need support from the TLB and memory system.

X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.

X86: Total overhaul of the division instructions and microops.

X86: Rework the multiplication microops so that they work like they would in the patent.

X86: Add floating point micro registers.

X86: Flesh out register indexing constants.

Add a spot for the condition code portion of the flag register.
This is stored in the integer register file so that it can be renamed, but it should be a misc reg.

Add in some microregs.

A new file for x86 specific parameters. This could be implemented as a sim object?