Searched refs:cpu_side (Results 1 - 22 of 22) sorted by relevance

/gem5/src/mem/
H A DMemChecker.py53 cpu_side = SlavePort("Alias for slave") variable in class:MemCheckerMonitor
/gem5/src/learning_gem5/part2/
H A DSimpleCache.py40 cpu_side = VectorSlavePort("CPU side port, receives requests") variable in class:SimpleCache
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py102 system.cpu.icache.cpu_side = system.cpu.icache_port
103 system.cpu.dcache.cpu_side = system.cpu.dcache_port
125 system.tol2bus.master = system.l2cache.cpu_side
/gem5/configs/learning_gem5/part1/
H A Dcaches.py91 self.cpu_side = cpu.icache_port
110 self.cpu_side = cpu.dcache_port
133 self.cpu_side = bus.master
/gem5/tests/configs/
H A Dmemtest.py54 system.l2c.cpu_side = system.toL2Bus.master
64 cpu.l1c.cpu_side = cpu.port
H A Dmemtest-filter.py55 system.l2c.cpu_side = system.toL2Bus.master
65 cpu.l1c.cpu_side = cpu.port
H A Dbase_config.py117 system.l2c.cpu_side = system.toL2Bus.master
293 system.llc[i].cpu_side = system.membus.master
297 system.iocache.cpu_side = system.iobus.master
/gem5/tests/gem5/memory/
H A Dmemtest-run.py55 system.l2c.cpu_side = system.toL2Bus.master
65 cpu.l1c.cpu_side = cpu.port
/gem5/util/tlm/conf/
H A Dtlm_elastic_slave.py95 system.cpu.icache.cpu_side = system.cpu.icache_port
96 system.cpu.dcache.cpu_side = system.cpu.dcache_port
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py66 # Since cpu_side is a vector port, each time one of these is connected, it will
68 system.cpu.icache_port = system.cache.cpu_side
69 system.cpu.dcache_port = system.cache.cpu_side
/gem5/configs/example/
H A Dmemtest.py271 xbar.master = next_cache.cpu_side
284 tester.port = cache.cpu_side
295 xbar.master = next_cache.cpu_side
300 testers[0].port = next_cache.cpu_side
314 last_subsys.xbar.master = system.llc.cpu_side
H A Dmemcheck.py263 xbar.master = next_cache.cpu_side
277 checker.master = cache.cpu_side
288 xbar.master = next_cache.cpu_side
295 checkers[0].master = next_cache.cpu_side
H A Dfs.py187 test_sys.iocache.cpu_side = test_sys.iobus.master
/gem5/tests/gem5/cpu_tests/
H A Drun.py63 self.cpu_side = cpu.icache_port
73 self.cpu_side = cpu.dcache_port
88 self.cpu_side = bus.master
/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py126 self.port = dc.cpu_side
/gem5/src/cpu/
H A DBaseCPU.py248 self.icache_port = ic.cpu_side
249 self.dcache_port = dc.cpu_side
255 self.itb.walker.port = iwc.cpu_side
256 self.dtb.walker.port = dwc.cpu_side
274 self.toL2Bus.master = self.l2cache.cpu_side
/gem5/src/mem/cache/
H A DCache.py113 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") variable in class:BaseCache
/gem5/configs/dram/
H A Dlat_mem_rd.py281 system.monitor.master = system.l1cache.cpu_side
286 system.l2cache.cpu_side = system.l2cache.xbar.master
293 system.l3cache.cpu_side = system.l3cache.xbar.master
/gem5/configs/example/arm/
H A Ddevices.py159 self.toL2Bus.master = self.l2.cpu_side
241 self.iocache.cpu_side = self.iobus.master
283 self.toL3Bus.master = self.l3.cpu_side
/gem5/configs/common/
H A DCacheConfig.py106 system.l2.cpu_side = system.tol2bus.master
146 dcache_mon.mem_side = dcache.cpu_side
208 # the connecting CPU SimObject wants to refer to its "cpu_side".
213 if (attr == "cpu_side"):
218 if (attr == "cpu_side"):
/gem5/configs/splash2/
H A Dcluster.py226 system.l2.cpu_side = system.toL2bus.slave
233 cluster.l1.cpu_side = cluster.clusterbus.master
H A Drun.py211 system.l2.cpu_side = system.toL2bus.master

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