1# Copyright (c) 2016-2017, 2019 ARM Limited
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3#
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35#
36# Authors: Andreas Sandberg
37#          Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41from __future__ import print_function
42from __future__ import absolute_import
43
44import m5
45from m5.objects import *
46m5.util.addToPath('../../')
47from common.Caches import *
48from common import CpuConfig
49
50have_kvm = "ArmV8KvmCPU" in CpuConfig.cpu_names()
51
52class L1I(L1_ICache):
53    tag_latency = 1
54    data_latency = 1
55    response_latency = 1
56    mshrs = 4
57    tgts_per_mshr = 8
58    size = '48kB'
59    assoc = 3
60
61
62class L1D(L1_DCache):
63    tag_latency = 2
64    data_latency = 2
65    response_latency = 1
66    mshrs = 16
67    tgts_per_mshr = 16
68    size = '32kB'
69    assoc = 2
70    write_buffers = 16
71
72
73class WalkCache(PageTableWalkerCache):
74    tag_latency = 4
75    data_latency = 4
76    response_latency = 4
77    mshrs = 6
78    tgts_per_mshr = 8
79    size = '1kB'
80    assoc = 8
81    write_buffers = 16
82
83
84class L2(L2Cache):
85    tag_latency = 12
86    data_latency = 12
87    response_latency = 5
88    mshrs = 32
89    tgts_per_mshr = 8
90    size = '1MB'
91    assoc = 16
92    write_buffers = 8
93    clusivity='mostly_excl'
94
95
96class L3(Cache):
97    size = '16MB'
98    assoc = 16
99    tag_latency = 20
100    data_latency = 20
101    response_latency = 20
102    mshrs = 20
103    tgts_per_mshr = 12
104    clusivity='mostly_excl'
105
106
107class MemBus(SystemXBar):
108    badaddr_responder = BadAddr(warn_access="warn")
109    default = Self.badaddr_responder.pio
110
111
112class CpuCluster(SubSystem):
113    def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
114                 cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
115        super(CpuCluster, self).__init__()
116        self._cpu_type = cpu_type
117        self._l1i_type = l1i_type
118        self._l1d_type = l1d_type
119        self._wcache_type = wcache_type
120        self._l2_type = l2_type
121
122        assert num_cpus > 0
123
124        self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
125        self.clk_domain = SrcClockDomain(clock=cpu_clock,
126                                         voltage_domain=self.voltage_domain)
127
128        self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
129                                     clk_domain=self.clk_domain)
130                      for idx in range(num_cpus) ]
131
132        for cpu in self.cpus:
133            cpu.createThreads()
134            cpu.createInterruptController()
135            cpu.socket_id = system.numCpuClusters()
136        system.addCpuCluster(self, num_cpus)
137
138    def requireCaches(self):
139        return self._cpu_type.require_caches()
140
141    def memoryMode(self):
142        return self._cpu_type.memory_mode()
143
144    def addL1(self):
145        for cpu in self.cpus:
146            l1i = None if self._l1i_type is None else self._l1i_type()
147            l1d = None if self._l1d_type is None else self._l1d_type()
148            iwc = None if self._wcache_type is None else self._wcache_type()
149            dwc = None if self._wcache_type is None else self._wcache_type()
150            cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
151
152    def addL2(self, clk_domain):
153        if self._l2_type is None:
154            return
155        self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
156        self.l2 = self._l2_type()
157        for cpu in self.cpus:
158            cpu.connectAllPorts(self.toL2Bus)
159        self.toL2Bus.master = self.l2.cpu_side
160
161    def connectMemSide(self, bus):
162        bus.slave
163        try:
164            self.l2.mem_side = bus.slave
165        except AttributeError:
166            for cpu in self.cpus:
167                cpu.connectAllPorts(bus)
168
169
170class AtomicCluster(CpuCluster):
171    def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
172        cpu_config = [ CpuConfig.get("AtomicSimpleCPU"), None, None, None, None ]
173        super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
174                                            cpu_voltage, *cpu_config)
175    def addL1(self):
176        pass
177
178class KvmCluster(CpuCluster):
179    def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
180        cpu_config = [ CpuConfig.get("ArmV8KvmCPU"), None, None, None, None ]
181        super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
182                                         cpu_voltage, *cpu_config)
183    def addL1(self):
184        pass
185
186
187class SimpleSystem(LinuxArmSystem):
188    cache_line_size = 64
189
190    def __init__(self, caches, mem_size, platform=None, **kwargs):
191        super(SimpleSystem, self).__init__(**kwargs)
192
193        self.voltage_domain = VoltageDomain(voltage="1.0V")
194        self.clk_domain = SrcClockDomain(clock="1GHz",
195                                         voltage_domain=Parent.voltage_domain)
196
197        if platform is None:
198            self.realview = VExpress_GEM5_V1()
199        else:
200            self.realview = platform
201
202        if hasattr(self.realview.gic, 'cpu_addr'):
203            self.gic_cpu_addr = self.realview.gic.cpu_addr
204        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
205
206        self.membus = MemBus()
207
208        self.intrctrl = IntrControl()
209        self.terminal = Terminal()
210        self.vncserver = VncServer()
211
212        self.iobus = IOXBar()
213        # CPUs->PIO
214        self.iobridge = Bridge(delay='50ns')
215        # Device DMA -> MEM
216        mem_range = self.realview._mem_regions[0]
217        assert long(mem_range.size()) >= long(Addr(mem_size))
218        self.mem_ranges = [ AddrRange(start=mem_range.start, size=mem_size) ]
219        self._caches = caches
220        if self._caches:
221            self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
222        else:
223            self.dmabridge = Bridge(delay='50ns',
224                                    ranges=[self.mem_ranges[0]])
225
226        self._pci_devices = 0
227        self._clusters = []
228        self._num_cpus = 0
229
230    def attach_pci(self, dev):
231        dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
232        self._pci_devices += 1
233        self.realview.attachPciDevice(dev, self.iobus)
234
235    def connect(self):
236        self.iobridge.master = self.iobus.slave
237        self.iobridge.slave = self.membus.master
238
239        if self._caches:
240            self.iocache.mem_side = self.membus.slave
241            self.iocache.cpu_side = self.iobus.master
242        else:
243            self.dmabridge.master = self.membus.slave
244            self.dmabridge.slave = self.iobus.master
245
246        if hasattr(self.realview.gic, 'cpu_addr'):
247            self.gic_cpu_addr = self.realview.gic.cpu_addr
248        self.realview.attachOnChipIO(self.membus, self.iobridge)
249        self.realview.attachIO(self.iobus)
250        self.system_port = self.membus.slave
251
252    def numCpuClusters(self):
253        return len(self._clusters)
254
255    def addCpuCluster(self, cpu_cluster, num_cpus):
256        assert cpu_cluster not in self._clusters
257        assert num_cpus > 0
258        self._clusters.append(cpu_cluster)
259        self._num_cpus += num_cpus
260
261    def numCpus(self):
262        return self._num_cpus
263
264    def addCaches(self, need_caches, last_cache_level):
265        if not need_caches:
266            # connect each cluster to the memory hierarchy
267            for cluster in self._clusters:
268                cluster.connectMemSide(self.membus)
269            return
270
271        cluster_mem_bus = self.membus
272        assert last_cache_level >= 1 and last_cache_level <= 3
273        for cluster in self._clusters:
274            cluster.addL1()
275        if last_cache_level > 1:
276            for cluster in self._clusters:
277                cluster.addL2(cluster.clk_domain)
278        if last_cache_level > 2:
279            max_clock_cluster = max(self._clusters,
280                                    key=lambda c: c.clk_domain.clock[0])
281            self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
282            self.toL3Bus = L2XBar(width=64)
283            self.toL3Bus.master = self.l3.cpu_side
284            self.l3.mem_side = self.membus.slave
285            cluster_mem_bus = self.toL3Bus
286
287        # connect each cluster to the memory hierarchy
288        for cluster in self._clusters:
289            cluster.connectMemSide(cluster_mem_bus)
290