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35#
36# Authors: Thomas Grass
37#          Andreas Hansson
38#          Sascha Bischoff
39
40from m5.params import *
41from m5.proxy import *
42from m5.objects.ClockedObject import ClockedObject
43
44# Types of Stream Generators.
45# Those are orthogonal to the other generators in the TrafficGen
46# and are meant to initialize the stream and substream IDs for
47# every memory request, regardless of how the packet has been
48# generated (Random, Linear, Trace etc)
49class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ]
50
51# The traffic generator is a master module that generates stimuli for
52# the memory system, based on a collection of simple behaviours that
53# are either probabilistic or based on traces. It can be used stand
54# alone for creating test cases for interconnect and memory
55# controllers, or function as a black-box replacement for system
56# components that are not yet modelled in detail, e.g. a video engine
57# or baseband subsystem in an SoC.
58class BaseTrafficGen(ClockedObject):
59    type = 'BaseTrafficGen'
60    abstract = True
61    cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
62
63    # Port used for sending requests and receiving responses
64    port = MasterPort("Master port")
65
66    # System used to determine the mode of the memory system
67    system = Param.System(Parent.any, "System this generator is part of")
68
69    # Should requests respond to back-pressure or not, if true, the
70    # rate of the traffic generator will be slowed down if requests
71    # are not immediately accepted
72    elastic_req = Param.Bool(False,
73                             "Slow down requests in case of backpressure")
74
75    # Maximum number of requests waiting for response. Set to 0 for an
76    # unlimited number of outstanding requests.
77    max_outstanding_reqs = Param.Int(0,
78                            "Maximum number of outstanding requests")
79
80    # Let the user know if we have waited for a retry and not made any
81    # progress for a long period of time. The default value is
82    # somewhat arbitrary and may well have to be tuned.
83    progress_check = Param.Latency('1ms', "Time before exiting " \
84                                   "due to lack of progress")
85
86    # Generator type used for applying Stream and/or Substream IDs to requests
87    stream_gen = Param.StreamGenType('none',
88        "Generator for adding Stream and/or Substream ID's to requests")
89
90    # Sources for Stream/Substream IDs to apply to requests
91    sids = VectorParam.Unsigned([], "StreamIDs to use")
92    ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
93
94    # These additional parameters allow TrafficGen to be used with scripts
95    # that expect a BaseCPU
96    cpu_id = Param.Int(-1, "CPU identifier")
97    socket_id = Param.Unsigned(0, "Physical Socket identifier")
98    numThreads = Param.Unsigned(1, "number of HW thread contexts")
99
100    @classmethod
101    def memory_mode(cls):
102        return 'timing'
103
104    @classmethod
105    def require_caches(cls):
106        return False
107
108    def createThreads(self):
109        pass
110
111    def createInterruptController(self):
112        pass
113
114    def connectCachedPorts(self, bus):
115        if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0):
116            for p in self._cached_ports:
117                exec('self.%s = bus.slave' % p)
118        else:
119            self.port = bus.slave
120
121    def connectAllPorts(self, cached_bus, uncached_bus = None):
122        self.connectCachedPorts(cached_bus)
123
124    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
125        self.dcache = dc
126        self.port = dc.cpu_side
127        self._cached_ports = ['dcache.mem_side']
128        self._uncached_ports = []
129