1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import m5
48from m5.objects import *
49from .Caches import *
50from . import HWPConfig
51
52def config_cache(options, system):
53    if options.external_memory_system and (options.caches or options.l2cache):
54        print("External caches and internal caches are exclusive options.\n")
55        sys.exit(1)
56
57    if options.external_memory_system:
58        ExternalCache = ExternalCacheFactory(options.external_memory_system)
59
60    if options.cpu_type == "O3_ARM_v7a_3":
61        try:
62            import cores.arm.O3_ARM_v7a as core
63        except:
64            print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
65            sys.exit(1)
66
67        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
68            core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
69            core.O3_ARM_v7aL2, \
70            core.O3_ARM_v7aWalkCache
71    elif options.cpu_type == "HPI":
72        try:
73            import cores.arm.HPI as core
74        except:
75            print("HPI is unavailable.")
76            sys.exit(1)
77
78        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
79            core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
80    else:
81        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
82            L1_DCache, L1_ICache, L2Cache, None
83
84        if buildEnv['TARGET_ISA'] == 'x86':
85            walk_cache_class = PageTableWalkerCache
86
87    # Set the cache line size of the system
88    system.cache_line_size = options.cacheline_size
89
90    # If elastic trace generation is enabled, make sure the memory system is
91    # minimal so that compute delays do not include memory access latencies.
92    # Configure the compulsory L1 caches for the O3CPU, do not configure
93    # any more caches.
94    if options.l2cache and options.elastic_trace_en:
95        fatal("When elastic trace is enabled, do not configure L2 caches.")
96
97    if options.l2cache:
98        # Provide a clock for the L2 and the L1-to-L2 bus here as they
99        # are not connected using addTwoLevelCacheHierarchy. Use the
100        # same clock as the CPUs.
101        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
102                                   size=options.l2_size,
103                                   assoc=options.l2_assoc)
104
105        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
106        system.l2.cpu_side = system.tol2bus.master
107        system.l2.mem_side = system.membus.slave
108        if options.l2_hwp_type:
109            hwpClass = HWPConfig.get(options.l2_hwp_type)
110            if system.l2.prefetcher != "Null":
111                print("Warning: l2-hwp-type is set (", hwpClass, "), but",
112                      "the current l2 has a default Hardware Prefetcher",
113                      "of type", type(system.l2.prefetcher), ", using the",
114                      "specified by the flag option.")
115            system.l2.prefetcher = hwpClass()
116
117    if options.memchecker:
118        system.memchecker = MemChecker()
119
120    for i in range(options.num_cpus):
121        if options.caches:
122            icache = icache_class(size=options.l1i_size,
123                                  assoc=options.l1i_assoc)
124            dcache = dcache_class(size=options.l1d_size,
125                                  assoc=options.l1d_assoc)
126
127            # If we have a walker cache specified, instantiate two
128            # instances here
129            if walk_cache_class:
130                iwalkcache = walk_cache_class()
131                dwalkcache = walk_cache_class()
132            else:
133                iwalkcache = None
134                dwalkcache = None
135
136            if options.memchecker:
137                dcache_mon = MemCheckerMonitor(warn_only=True)
138                dcache_real = dcache
139
140                # Do not pass the memchecker into the constructor of
141                # MemCheckerMonitor, as it would create a copy; we require
142                # exactly one MemChecker instance.
143                dcache_mon.memchecker = system.memchecker
144
145                # Connect monitor
146                dcache_mon.mem_side = dcache.cpu_side
147
148                # Let CPU connect to monitors
149                dcache = dcache_mon
150
151            if options.l1d_hwp_type:
152                hwpClass = HWPConfig.get(options.l1d_hwp_type)
153                if dcache.prefetcher != m5.params.NULL:
154                    print("Warning: l1d-hwp-type is set (", hwpClass, "), but",
155                          "the current l1d has a default Hardware Prefetcher",
156                          "of type", type(dcache.prefetcher), ", using the",
157                          "specified by the flag option.")
158                dcache.prefetcher = hwpClass()
159
160            if options.l1i_hwp_type:
161                hwpClass = HWPConfig.get(options.l1i_hwp_type)
162                if icache.prefetcher != m5.params.NULL:
163                    print("Warning: l1i-hwp-type is set (", hwpClass, "), but",
164                          "the current l1i has a default Hardware Prefetcher",
165                          "of type", type(icache.prefetcher), ", using the",
166                          "specified by the flag option.")
167                icache.prefetcher = hwpClass()
168
169            # When connecting the caches, the clock is also inherited
170            # from the CPU in question
171            system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
172                                                  iwalkcache, dwalkcache)
173
174            if options.memchecker:
175                # The mem_side ports of the caches haven't been connected yet.
176                # Make sure connectAllPorts connects the right objects.
177                system.cpu[i].dcache = dcache_real
178                system.cpu[i].dcache_mon = dcache_mon
179
180        elif options.external_memory_system:
181            # These port names are presented to whatever 'external' system
182            # gem5 is connecting to.  Its configuration will likely depend
183            # on these names.  For simplicity, we would advise configuring
184            # it to use this naming scheme; if this isn't possible, change
185            # the names below.
186            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
187                system.cpu[i].addPrivateSplitL1Caches(
188                        ExternalCache("cpu%d.icache" % i),
189                        ExternalCache("cpu%d.dcache" % i),
190                        ExternalCache("cpu%d.itb_walker_cache" % i),
191                        ExternalCache("cpu%d.dtb_walker_cache" % i))
192            else:
193                system.cpu[i].addPrivateSplitL1Caches(
194                        ExternalCache("cpu%d.icache" % i),
195                        ExternalCache("cpu%d.dcache" % i))
196
197        system.cpu[i].createInterruptController()
198        if options.l2cache:
199            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
200        elif options.external_memory_system:
201            system.cpu[i].connectUncachedPorts(system.membus)
202        else:
203            system.cpu[i].connectAllPorts(system.membus)
204
205    return system
206
207# ExternalSlave provides a "port", but when that port connects to a cache,
208# the connecting CPU SimObject wants to refer to its "cpu_side".
209# The 'ExternalCache' class provides this adaptation by rewriting the name,
210# eliminating distracting changes elsewhere in the config code.
211class ExternalCache(ExternalSlave):
212    def __getattr__(cls, attr):
213        if (attr == "cpu_side"):
214            attr = "port"
215        return super(ExternalSlave, cls).__getattr__(attr)
216
217    def __setattr__(cls, attr, value):
218        if (attr == "cpu_side"):
219            attr = "port"
220        return super(ExternalSlave, cls).__setattr__(attr, value)
221
222def ExternalCacheFactory(port_type):
223    def make(name):
224        return ExternalCache(port_data=name, port_type=port_type,
225                             addr_ranges=[AllMemory])
226    return make
227