114053Stiago.muck@arm.com# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
212810Sandreas.sandberg@arm.com# All rights reserved.
312810Sandreas.sandberg@arm.com#
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612810Sandreas.sandberg@arm.com# property including but not limited to intellectual property relating
712810Sandreas.sandberg@arm.com# to a hardware implementation of the functionality of the software
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3512810Sandreas.sandberg@arm.com#
3612810Sandreas.sandberg@arm.com# Authors: Thomas Grass
3712810Sandreas.sandberg@arm.com#          Andreas Hansson
3812810Sandreas.sandberg@arm.com#          Sascha Bischoff
3912810Sandreas.sandberg@arm.com
4012810Sandreas.sandberg@arm.comfrom m5.params import *
4112810Sandreas.sandberg@arm.comfrom m5.proxy import *
4213892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject
4312810Sandreas.sandberg@arm.com
4412919Sgiacomo.travaglini@arm.com# Types of Stream Generators.
4512919Sgiacomo.travaglini@arm.com# Those are orthogonal to the other generators in the TrafficGen
4612919Sgiacomo.travaglini@arm.com# and are meant to initialize the stream and substream IDs for
4712919Sgiacomo.travaglini@arm.com# every memory request, regardless of how the packet has been
4812919Sgiacomo.travaglini@arm.com# generated (Random, Linear, Trace etc)
4912919Sgiacomo.travaglini@arm.comclass StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ]
5012919Sgiacomo.travaglini@arm.com
5112810Sandreas.sandberg@arm.com# The traffic generator is a master module that generates stimuli for
5212810Sandreas.sandberg@arm.com# the memory system, based on a collection of simple behaviours that
5312810Sandreas.sandberg@arm.com# are either probabilistic or based on traces. It can be used stand
5412810Sandreas.sandberg@arm.com# alone for creating test cases for interconnect and memory
5512810Sandreas.sandberg@arm.com# controllers, or function as a black-box replacement for system
5612810Sandreas.sandberg@arm.com# components that are not yet modelled in detail, e.g. a video engine
5712810Sandreas.sandberg@arm.com# or baseband subsystem in an SoC.
5813892Sgabeblack@google.comclass BaseTrafficGen(ClockedObject):
5912810Sandreas.sandberg@arm.com    type = 'BaseTrafficGen'
6012810Sandreas.sandberg@arm.com    abstract = True
6112810Sandreas.sandberg@arm.com    cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
6212810Sandreas.sandberg@arm.com
6312810Sandreas.sandberg@arm.com    # Port used for sending requests and receiving responses
6412810Sandreas.sandberg@arm.com    port = MasterPort("Master port")
6512810Sandreas.sandberg@arm.com
6612810Sandreas.sandberg@arm.com    # System used to determine the mode of the memory system
6712810Sandreas.sandberg@arm.com    system = Param.System(Parent.any, "System this generator is part of")
6812810Sandreas.sandberg@arm.com
6912810Sandreas.sandberg@arm.com    # Should requests respond to back-pressure or not, if true, the
7012810Sandreas.sandberg@arm.com    # rate of the traffic generator will be slowed down if requests
7112810Sandreas.sandberg@arm.com    # are not immediately accepted
7212810Sandreas.sandberg@arm.com    elastic_req = Param.Bool(False,
7312810Sandreas.sandberg@arm.com                             "Slow down requests in case of backpressure")
7412810Sandreas.sandberg@arm.com
7514054Stiago.muck@arm.com    # Maximum number of requests waiting for response. Set to 0 for an
7614054Stiago.muck@arm.com    # unlimited number of outstanding requests.
7714054Stiago.muck@arm.com    max_outstanding_reqs = Param.Int(0,
7814054Stiago.muck@arm.com                            "Maximum number of outstanding requests")
7914054Stiago.muck@arm.com
8012810Sandreas.sandberg@arm.com    # Let the user know if we have waited for a retry and not made any
8112810Sandreas.sandberg@arm.com    # progress for a long period of time. The default value is
8212810Sandreas.sandberg@arm.com    # somewhat arbitrary and may well have to be tuned.
8312810Sandreas.sandberg@arm.com    progress_check = Param.Latency('1ms', "Time before exiting " \
8412810Sandreas.sandberg@arm.com                                   "due to lack of progress")
8512919Sgiacomo.travaglini@arm.com
8612919Sgiacomo.travaglini@arm.com    # Generator type used for applying Stream and/or Substream IDs to requests
8712919Sgiacomo.travaglini@arm.com    stream_gen = Param.StreamGenType('none',
8812919Sgiacomo.travaglini@arm.com        "Generator for adding Stream and/or Substream ID's to requests")
8912919Sgiacomo.travaglini@arm.com
9012919Sgiacomo.travaglini@arm.com    # Sources for Stream/Substream IDs to apply to requests
9112919Sgiacomo.travaglini@arm.com    sids = VectorParam.Unsigned([], "StreamIDs to use")
9212919Sgiacomo.travaglini@arm.com    ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
9314053Stiago.muck@arm.com
9414053Stiago.muck@arm.com    # These additional parameters allow TrafficGen to be used with scripts
9514053Stiago.muck@arm.com    # that expect a BaseCPU
9614053Stiago.muck@arm.com    cpu_id = Param.Int(-1, "CPU identifier")
9714053Stiago.muck@arm.com    socket_id = Param.Unsigned(0, "Physical Socket identifier")
9814053Stiago.muck@arm.com    numThreads = Param.Unsigned(1, "number of HW thread contexts")
9914053Stiago.muck@arm.com
10014053Stiago.muck@arm.com    @classmethod
10114053Stiago.muck@arm.com    def memory_mode(cls):
10214053Stiago.muck@arm.com        return 'timing'
10314053Stiago.muck@arm.com
10414053Stiago.muck@arm.com    @classmethod
10514053Stiago.muck@arm.com    def require_caches(cls):
10614053Stiago.muck@arm.com        return False
10714053Stiago.muck@arm.com
10814053Stiago.muck@arm.com    def createThreads(self):
10914053Stiago.muck@arm.com        pass
11014053Stiago.muck@arm.com
11114053Stiago.muck@arm.com    def createInterruptController(self):
11214053Stiago.muck@arm.com        pass
11314053Stiago.muck@arm.com
11414053Stiago.muck@arm.com    def connectCachedPorts(self, bus):
11514053Stiago.muck@arm.com        if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0):
11614053Stiago.muck@arm.com            for p in self._cached_ports:
11714053Stiago.muck@arm.com                exec('self.%s = bus.slave' % p)
11814053Stiago.muck@arm.com        else:
11914053Stiago.muck@arm.com            self.port = bus.slave
12014053Stiago.muck@arm.com
12114053Stiago.muck@arm.com    def connectAllPorts(self, cached_bus, uncached_bus = None):
12214053Stiago.muck@arm.com        self.connectCachedPorts(cached_bus)
12314053Stiago.muck@arm.com
12414053Stiago.muck@arm.com    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
12514053Stiago.muck@arm.com        self.dcache = dc
12614053Stiago.muck@arm.com        self.port = dc.cpu_side
12714053Stiago.muck@arm.com        self._cached_ports = ['dcache.mem_side']
12814053Stiago.muck@arm.com        self._uncached_ports = []
129