1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Jason Power
29
30""" Caches with options for a simple gem5 configuration script
31
32This file contains L1 I/D and L2 caches to be used in the simple
33gem5 configuration script. It uses the SimpleOpts wrapper to set up command
34line options from each individual class.
35"""
36
37from __future__ import print_function
38from __future__ import absolute_import
39
40import m5
41from m5.objects import Cache
42
43# Add the common scripts to our path
44m5.util.addToPath('../../')
45
46from common import SimpleOpts
47
48# Some specific options for caches
49# For all options see src/mem/cache/BaseCache.py
50
51class L1Cache(Cache):
52    """Simple L1 Cache with default values"""
53
54    assoc = 2
55    tag_latency = 2
56    data_latency = 2
57    response_latency = 2
58    mshrs = 4
59    tgts_per_mshr = 20
60
61    def __init__(self, options=None):
62        super(L1Cache, self).__init__()
63        pass
64
65    def connectBus(self, bus):
66        """Connect this cache to a memory-side bus"""
67        self.mem_side = bus.slave
68
69    def connectCPU(self, cpu):
70        """Connect this cache's port to a CPU-side port
71           This must be defined in a subclass"""
72        raise NotImplementedError
73
74class L1ICache(L1Cache):
75    """Simple L1 instruction cache with default values"""
76
77    # Set the default size
78    size = '16kB'
79
80    SimpleOpts.add_option('--l1i_size',
81                          help="L1 instruction cache size. Default: %s" % size)
82
83    def __init__(self, opts=None):
84        super(L1ICache, self).__init__(opts)
85        if not opts or not opts.l1i_size:
86            return
87        self.size = opts.l1i_size
88
89    def connectCPU(self, cpu):
90        """Connect this cache's port to a CPU icache port"""
91        self.cpu_side = cpu.icache_port
92
93class L1DCache(L1Cache):
94    """Simple L1 data cache with default values"""
95
96    # Set the default size
97    size = '64kB'
98
99    SimpleOpts.add_option('--l1d_size',
100                          help="L1 data cache size. Default: %s" % size)
101
102    def __init__(self, opts=None):
103        super(L1DCache, self).__init__(opts)
104        if not opts or not opts.l1d_size:
105            return
106        self.size = opts.l1d_size
107
108    def connectCPU(self, cpu):
109        """Connect this cache's port to a CPU dcache port"""
110        self.cpu_side = cpu.dcache_port
111
112class L2Cache(Cache):
113    """Simple L2 Cache with default values"""
114
115    # Default parameters
116    size = '256kB'
117    assoc = 8
118    tag_latency = 20
119    data_latency = 20
120    response_latency = 20
121    mshrs = 20
122    tgts_per_mshr = 12
123
124    SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
125
126    def __init__(self, opts=None):
127        super(L2Cache, self).__init__()
128        if not opts or not opts.l2_size:
129            return
130        self.size = opts.l2_size
131
132    def connectCPUSideBus(self, bus):
133        self.cpu_side = bus.master
134
135    def connectMemSideBus(self, bus):
136        self.mem_side = bus.slave
137