111752Snikos.nikoleris@arm.com# Copyright (c) 2015-2016 ARM Limited 210705Sandreas.hansson@arm.com# All rights reserved. 310705Sandreas.hansson@arm.com# 410705Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510705Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610705Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710705Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810705Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910705Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010705Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110705Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210705Sandreas.hansson@arm.com# 1310705Sandreas.hansson@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1410705Sandreas.hansson@arm.com# All rights reserved. 1510705Sandreas.hansson@arm.com# 1610705Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 1710705Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 1810705Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 1910705Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 2010705Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 2110705Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 2210705Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 2310705Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 2410705Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 2510705Sandreas.hansson@arm.com# this software without specific prior written permission. 2610705Sandreas.hansson@arm.com# 2710705Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810705Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910705Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010705Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110705Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210705Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310705Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410705Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510705Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610705Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710705Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810705Sandreas.hansson@arm.com# 3910705Sandreas.hansson@arm.com# Authors: Ron Dreslinski 4010705Sandreas.hansson@arm.com# Andreas Hansson 4110705Sandreas.hansson@arm.com 4212564Sgabeblack@google.comfrom __future__ import print_function 4313774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 4412564Sgabeblack@google.com 4510705Sandreas.hansson@arm.comimport optparse 4611753Snikos.nikoleris@arm.comimport random 4710705Sandreas.hansson@arm.comimport sys 4810705Sandreas.hansson@arm.com 4910705Sandreas.hansson@arm.comimport m5 5010705Sandreas.hansson@arm.comfrom m5.objects import * 5110705Sandreas.hansson@arm.com 5210705Sandreas.hansson@arm.comparser = optparse.OptionParser() 5310705Sandreas.hansson@arm.com 5410705Sandreas.hansson@arm.comparser.add_option("-a", "--atomic", action="store_true", 5510705Sandreas.hansson@arm.com help="Use atomic (non-timing) mode") 5610705Sandreas.hansson@arm.comparser.add_option("-b", "--blocking", action="store_true", 5710705Sandreas.hansson@arm.com help="Use blocking caches") 5810705Sandreas.hansson@arm.comparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 5910705Sandreas.hansson@arm.com metavar="T", 6010705Sandreas.hansson@arm.com help="Stop after T ticks") 6110705Sandreas.hansson@arm.comparser.add_option("-p", "--prefetchers", action="store_true", 6210705Sandreas.hansson@arm.com help="Use prefetchers") 6310705Sandreas.hansson@arm.comparser.add_option("-s", "--stridepref", action="store_true", 6410705Sandreas.hansson@arm.com help="Use strided prefetchers") 6510705Sandreas.hansson@arm.com 6610705Sandreas.hansson@arm.com# This example script has a lot in common with the memtest.py in that 6710705Sandreas.hansson@arm.com# it is designed to stress tests the memory system. However, this 6810705Sandreas.hansson@arm.com# script uses oblivious traffic generators to create the stimuli, and 6910705Sandreas.hansson@arm.com# couples them with memcheckers to verify that the data read matches 7010705Sandreas.hansson@arm.com# the allowed outcomes. Just like memtest.py, the traffic generators 7110705Sandreas.hansson@arm.com# and checkers are placed in a tree topology. At the bottom of the 7210705Sandreas.hansson@arm.com# tree is a shared memory, and then at each level a number of 7310705Sandreas.hansson@arm.com# generators and checkers are attached, along with a number of caches 7410705Sandreas.hansson@arm.com# that them selves fan out to subtrees of generators and caches. Thus, 7510705Sandreas.hansson@arm.com# it is possible to create a system with arbitrarily deep cache 7610705Sandreas.hansson@arm.com# hierarchies, sharing or no sharing of caches, and generators not 7710705Sandreas.hansson@arm.com# only at the L1s, but also at the L2s, L3s etc. 7810705Sandreas.hansson@arm.com# 7910705Sandreas.hansson@arm.com# The tree specification consists of two colon-separated lists of one 8010705Sandreas.hansson@arm.com# or more integers, one for the caches, and one for the 8110705Sandreas.hansson@arm.com# testers/generators. The first integer is the number of 8210705Sandreas.hansson@arm.com# caches/testers closest to main memory. Each cache then fans out to a 8310705Sandreas.hansson@arm.com# subtree. The last integer in the list is the number of 8410705Sandreas.hansson@arm.com# caches/testers associated with the uppermost level of memory. The 8510705Sandreas.hansson@arm.com# other integers (if any) specify the number of caches/testers 8610705Sandreas.hansson@arm.com# connected at each level of the crossbar hierarchy. The tester string 8710705Sandreas.hansson@arm.com# should have one element more than the cache string as there should 8810705Sandreas.hansson@arm.com# always be testers attached to the uppermost caches. 8910705Sandreas.hansson@arm.com# 9010705Sandreas.hansson@arm.com# Since this script tests actual sharing, there is also a possibility 9110705Sandreas.hansson@arm.com# to stress prefetching and the interaction between prefetchers and 9210705Sandreas.hansson@arm.com# caches. The traffic generators switch between random address streams 9310705Sandreas.hansson@arm.com# and linear address streams to ensure that the prefetchers will 9410705Sandreas.hansson@arm.com# trigger. By default prefetchers are off. 9510705Sandreas.hansson@arm.com 9610705Sandreas.hansson@arm.comparser.add_option("-c", "--caches", type="string", default="3:2", 9710705Sandreas.hansson@arm.com help="Colon-separated cache hierarchy specification, " 9810705Sandreas.hansson@arm.com "see script comments for details " 9910705Sandreas.hansson@arm.com "[default: %default]") 10010705Sandreas.hansson@arm.comparser.add_option("-t", "--testers", type="string", default="1:0:2", 10110705Sandreas.hansson@arm.com help="Colon-separated tester hierarchy specification, " 10210705Sandreas.hansson@arm.com "see script comments for details " 10310705Sandreas.hansson@arm.com "[default: %default]") 10411753Snikos.nikoleris@arm.comparser.add_option("-r", "--random", action="store_true", 10511753Snikos.nikoleris@arm.com help="Generate a random tree topology") 10610705Sandreas.hansson@arm.comparser.add_option("--sys-clock", action="store", type="string", 10710705Sandreas.hansson@arm.com default='1GHz', 10810705Sandreas.hansson@arm.com help = """Top-level clock for blocks running at system 10910705Sandreas.hansson@arm.com speed""") 11010705Sandreas.hansson@arm.com 11110705Sandreas.hansson@arm.com(options, args) = parser.parse_args() 11210705Sandreas.hansson@arm.com 11310705Sandreas.hansson@arm.comif args: 11412564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 11510705Sandreas.hansson@arm.com sys.exit(1) 11610705Sandreas.hansson@arm.com 11710705Sandreas.hansson@arm.com# Start by parsing the command line options and do some basic sanity 11810705Sandreas.hansson@arm.com# checking 11911753Snikos.nikoleris@arm.comif options.random: 12011753Snikos.nikoleris@arm.com # Generate a tree with a valid number of testers 12111753Snikos.nikoleris@arm.com tree_depth = random.randint(1, 4) 12211753Snikos.nikoleris@arm.com cachespec = [random.randint(1, 3) for i in range(tree_depth)] 12311753Snikos.nikoleris@arm.com testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 12412564Sgabeblack@google.com print("Generated random tree -c", ':'.join(map(str, cachespec)), 12512564Sgabeblack@google.com "-t", ':'.join(map(str, testerspec))) 12611753Snikos.nikoleris@arm.comelse: 12711753Snikos.nikoleris@arm.com try: 12811753Snikos.nikoleris@arm.com cachespec = [int(x) for x in options.caches.split(':')] 12911753Snikos.nikoleris@arm.com testerspec = [int(x) for x in options.testers.split(':')] 13011753Snikos.nikoleris@arm.com except: 13112564Sgabeblack@google.com print("Error: Unable to parse caches or testers option") 13210705Sandreas.hansson@arm.com sys.exit(1) 13310705Sandreas.hansson@arm.com 13411753Snikos.nikoleris@arm.com if len(cachespec) < 1: 13512564Sgabeblack@google.com print("Error: Must have at least one level of caches") 13610705Sandreas.hansson@arm.com sys.exit(1) 13710705Sandreas.hansson@arm.com 13811753Snikos.nikoleris@arm.com if len(cachespec) != len(testerspec) - 1: 13912564Sgabeblack@google.com print("Error: Testers must have one element more than caches") 14011753Snikos.nikoleris@arm.com sys.exit(1) 14111753Snikos.nikoleris@arm.com 14211753Snikos.nikoleris@arm.com if testerspec[-1] == 0: 14312564Sgabeblack@google.com print("Error: Must have testers at the uppermost level") 14411753Snikos.nikoleris@arm.com sys.exit(1) 14511753Snikos.nikoleris@arm.com 14611753Snikos.nikoleris@arm.com for t in testerspec: 14711753Snikos.nikoleris@arm.com if t < 0: 14812564Sgabeblack@google.com print("Error: Cannot have a negative number of testers") 14911753Snikos.nikoleris@arm.com sys.exit(1) 15011753Snikos.nikoleris@arm.com 15111753Snikos.nikoleris@arm.com for c in cachespec: 15211753Snikos.nikoleris@arm.com if c < 1: 15312564Sgabeblack@google.com print("Error: Must have 1 or more caches at each level") 15411753Snikos.nikoleris@arm.com sys.exit(1) 15511753Snikos.nikoleris@arm.com 15610705Sandreas.hansson@arm.com# Determine the tester multiplier for each level as the string 15710705Sandreas.hansson@arm.com# elements are per subsystem and it fans out 15810705Sandreas.hansson@arm.commultiplier = [1] 15910705Sandreas.hansson@arm.comfor c in cachespec: 16010705Sandreas.hansson@arm.com if c < 1: 16112564Sgabeblack@google.com print("Error: Must have at least one cache per level") 16210705Sandreas.hansson@arm.com multiplier.append(multiplier[-1] * c) 16310705Sandreas.hansson@arm.com 16410705Sandreas.hansson@arm.comnumtesters = 0 16510705Sandreas.hansson@arm.comfor t, m in zip(testerspec, multiplier): 16610705Sandreas.hansson@arm.com numtesters += t * m 16710705Sandreas.hansson@arm.com 16810705Sandreas.hansson@arm.com# Define a prototype L1 cache that we scale for all successive levels 16911053Sandreas.hansson@arm.comproto_l1 = Cache(size = '32kB', assoc = 4, 17011722Ssophiane.senni@gmail.com tag_latency = 1, data_latency = 1, response_latency = 1, 17111053Sandreas.hansson@arm.com tgts_per_mshr = 8) 17210705Sandreas.hansson@arm.com 17310705Sandreas.hansson@arm.comif options.blocking: 17410705Sandreas.hansson@arm.com proto_l1.mshrs = 1 17510705Sandreas.hansson@arm.comelse: 17610705Sandreas.hansson@arm.com proto_l1.mshrs = 4 17710705Sandreas.hansson@arm.com 17810705Sandreas.hansson@arm.comif options.prefetchers: 17910705Sandreas.hansson@arm.com proto_l1.prefetcher = TaggedPrefetcher() 18010705Sandreas.hansson@arm.comelif options.stridepref: 18110705Sandreas.hansson@arm.com proto_l1.prefetcher = StridePrefetcher() 18210705Sandreas.hansson@arm.com 18310705Sandreas.hansson@arm.comcache_proto = [proto_l1] 18410705Sandreas.hansson@arm.com 18510705Sandreas.hansson@arm.com# Now add additional cache levels (if any) by scaling L1 params, the 18610705Sandreas.hansson@arm.com# first element is Ln, and the last element L1 18710705Sandreas.hansson@arm.comfor scale in cachespec[:-1]: 18810705Sandreas.hansson@arm.com # Clone previous level and update params 18910705Sandreas.hansson@arm.com prev = cache_proto[0] 19010705Sandreas.hansson@arm.com next = prev() 19110705Sandreas.hansson@arm.com next.size = prev.size * scale 19211722Ssophiane.senni@gmail.com next.tag_latency = prev.tag_latency * 10 19311722Ssophiane.senni@gmail.com next.data_latency = prev.data_latency * 10 19410705Sandreas.hansson@arm.com next.response_latency = prev.response_latency * 10 19510705Sandreas.hansson@arm.com next.assoc = prev.assoc * scale 19610705Sandreas.hansson@arm.com next.mshrs = prev.mshrs * scale 19710705Sandreas.hansson@arm.com cache_proto.insert(0, next) 19810705Sandreas.hansson@arm.com 19910705Sandreas.hansson@arm.com# Create a config to be used by all the traffic generators 20010705Sandreas.hansson@arm.comcfg_file_name = "configs/example/memcheck.cfg" 20110705Sandreas.hansson@arm.comcfg_file = open(cfg_file_name, 'w') 20210705Sandreas.hansson@arm.com 20310705Sandreas.hansson@arm.com# Three states, with random, linear and idle behaviours. The random 20410705Sandreas.hansson@arm.com# and linear states access memory in the range [0 : 16 Mbyte] with 8 20511752Snikos.nikoleris@arm.com# byte and 64 byte accesses respectively. 20610705Sandreas.hansson@arm.comcfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n") 20711752Snikos.nikoleris@arm.comcfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n") 20810705Sandreas.hansson@arm.comcfg_file.write("STATE 2 10000000 IDLE\n") 20910705Sandreas.hansson@arm.comcfg_file.write("INIT 0\n") 21010705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 0 1 0.5\n") 21110705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 0 2 0.5\n") 21210705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 1 0 0.5\n") 21310705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 1 2 0.5\n") 21410705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 2 0 0.5\n") 21510705Sandreas.hansson@arm.comcfg_file.write("TRANSITION 2 1 0.5\n") 21610705Sandreas.hansson@arm.comcfg_file.close() 21710705Sandreas.hansson@arm.com 21810705Sandreas.hansson@arm.com# Make a prototype for the tester to be used throughout 21910705Sandreas.hansson@arm.comproto_tester = TrafficGen(config_file = cfg_file_name) 22010705Sandreas.hansson@arm.com 22110705Sandreas.hansson@arm.com# Set up the system along with a DRAM controller 22211837Swendy.elsasser@arm.comsystem = System(physmem = DDR3_1600_8x8()) 22310705Sandreas.hansson@arm.com 22410705Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = '1V') 22510705Sandreas.hansson@arm.com 22610705Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 22710705Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 22810705Sandreas.hansson@arm.com 22910705Sandreas.hansson@arm.comsystem.memchecker = MemChecker() 23010705Sandreas.hansson@arm.com 23110705Sandreas.hansson@arm.com# For each level, track the next subsys index to use 23210705Sandreas.hansson@arm.comnext_subsys_index = [0] * (len(cachespec) + 1) 23310705Sandreas.hansson@arm.com 23410705Sandreas.hansson@arm.com# Recursive function to create a sub-tree of the cache and tester 23510705Sandreas.hansson@arm.com# hierarchy 23610705Sandreas.hansson@arm.comdef make_cache_level(ncaches, prototypes, level, next_cache): 23710705Sandreas.hansson@arm.com global next_subsys_index, proto_l1, testerspec, proto_tester 23810705Sandreas.hansson@arm.com 23910705Sandreas.hansson@arm.com index = next_subsys_index[level] 24010705Sandreas.hansson@arm.com next_subsys_index[level] += 1 24110705Sandreas.hansson@arm.com 24210705Sandreas.hansson@arm.com # Create a subsystem to contain the crossbar and caches, and 24310705Sandreas.hansson@arm.com # any testers 24410705Sandreas.hansson@arm.com subsys = SubSystem() 24510705Sandreas.hansson@arm.com setattr(system, 'l%dsubsys%d' % (level, index), subsys) 24610705Sandreas.hansson@arm.com 24710705Sandreas.hansson@arm.com # The levels are indexing backwards through the list 24810705Sandreas.hansson@arm.com ntesters = testerspec[len(cachespec) - level] 24910705Sandreas.hansson@arm.com 25013731Sandreas.sandberg@arm.com testers = [proto_tester() for i in range(ntesters)] 25110705Sandreas.hansson@arm.com checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ 25213731Sandreas.sandberg@arm.com for i in range(ntesters)] 25310705Sandreas.hansson@arm.com if ntesters: 25410705Sandreas.hansson@arm.com subsys.tester = testers 25510705Sandreas.hansson@arm.com subsys.checkers = checkers 25610705Sandreas.hansson@arm.com 25710705Sandreas.hansson@arm.com if level != 0: 25810705Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem, note that 25910705Sandreas.hansson@arm.com # we do this even with a single element on this level 26010720Sandreas.hansson@arm.com xbar = L2XBar(width = 32) 26110705Sandreas.hansson@arm.com subsys.xbar = xbar 26210705Sandreas.hansson@arm.com if next_cache: 26310705Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 26410705Sandreas.hansson@arm.com 26510705Sandreas.hansson@arm.com # Create and connect the caches, both the ones fanning out 26610705Sandreas.hansson@arm.com # to create the tree, and the ones used to connect testers 26710705Sandreas.hansson@arm.com # on this level 26813731Sandreas.sandberg@arm.com tree_caches = [prototypes[0]() for i in range(ncaches[0])] 26913731Sandreas.sandberg@arm.com tester_caches = [proto_l1() for i in range(ntesters)] 27010705Sandreas.hansson@arm.com 27110705Sandreas.hansson@arm.com subsys.cache = tester_caches + tree_caches 27210705Sandreas.hansson@arm.com for cache in tree_caches: 27310705Sandreas.hansson@arm.com cache.mem_side = xbar.slave 27410705Sandreas.hansson@arm.com make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 27510705Sandreas.hansson@arm.com for tester, checker, cache in zip(testers, checkers, tester_caches): 27610705Sandreas.hansson@arm.com tester.port = checker.slave 27710705Sandreas.hansson@arm.com checker.master = cache.cpu_side 27810705Sandreas.hansson@arm.com cache.mem_side = xbar.slave 27910705Sandreas.hansson@arm.com else: 28010705Sandreas.hansson@arm.com if not next_cache: 28112564Sgabeblack@google.com print("Error: No next-level cache at top level") 28210705Sandreas.hansson@arm.com sys.exit(1) 28310705Sandreas.hansson@arm.com 28410705Sandreas.hansson@arm.com if ntesters > 1: 28510705Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem 28610720Sandreas.hansson@arm.com xbar = L2XBar(width = 32) 28710705Sandreas.hansson@arm.com subsys.xbar = xbar 28810705Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 28910705Sandreas.hansson@arm.com for tester, checker in zip(testers, checkers): 29010705Sandreas.hansson@arm.com tester.port = checker.slave 29110705Sandreas.hansson@arm.com checker.master = xbar.slave 29210705Sandreas.hansson@arm.com else: 29310705Sandreas.hansson@arm.com # Single tester 29410705Sandreas.hansson@arm.com testers[0].port = checkers[0].slave 29510705Sandreas.hansson@arm.com checkers[0].master = next_cache.cpu_side 29610705Sandreas.hansson@arm.com 29710705Sandreas.hansson@arm.com# Top level call to create the cache hierarchy, bottom up 29810705Sandreas.hansson@arm.commake_cache_level(cachespec, cache_proto, len(cachespec), None) 29910705Sandreas.hansson@arm.com 30010705Sandreas.hansson@arm.com# Connect the lowest level crossbar to the memory 30110705Sandreas.hansson@arm.comlast_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 30210705Sandreas.hansson@arm.comlast_subsys.xbar.master = system.physmem.port 30311451Sandreas.hansson@arm.comlast_subsys.xbar.point_of_coherency = True 30410705Sandreas.hansson@arm.com 30510705Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 30610705Sandreas.hansson@arm.comif options.atomic: 30710705Sandreas.hansson@arm.com root.system.mem_mode = 'atomic' 30810705Sandreas.hansson@arm.comelse: 30910705Sandreas.hansson@arm.com root.system.mem_mode = 'timing' 31010705Sandreas.hansson@arm.com 31110705Sandreas.hansson@arm.com# The system port is never used in the tester so merely connect it 31210705Sandreas.hansson@arm.com# to avoid problems 31310705Sandreas.hansson@arm.comroot.system.system_port = last_subsys.xbar.slave 31410705Sandreas.hansson@arm.com 31510705Sandreas.hansson@arm.com# Instantiate configuration 31610705Sandreas.hansson@arm.comm5.instantiate() 31710705Sandreas.hansson@arm.com 31810705Sandreas.hansson@arm.com# Simulate until program terminates 31910705Sandreas.hansson@arm.comexit_event = m5.simulate(options.maxtick) 32010705Sandreas.hansson@arm.com 32112564Sgabeblack@google.comprint('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 322