/gem5/src/systemc/tests/systemc/misc/sim_tests/tri_state2/ |
H A D | display.h | 47 const sc_signal_resolved& bus; //input local 52 : bus(BUS) 55 sensitive << bus; local
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H A D | display.cpp | 45 cout << "Value on Bus = " << bus.read() << endl;
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H A D | main.cpp | 47 sc_signal_resolved bus; local 53 driver D("Driver", clock, bus, control, out); 54 ts_buf B("Buffer", out, control, bus); 55 pullup P("BusPullup", clock, bus); 56 display DISP("BusDisplay", bus);
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/gem5/src/systemc/tests/systemc/misc/user_guide/chpt6.1/ |
H A D | display.h | 47 const signal_std_logic& bus; //input local 52 : bus(BUS) 56 sensitive << bus; local
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H A D | display.cpp | 45 cout << "Value on Bus = " << bus.read() << endl;
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H A D | main.cpp | 46 signal_std_logic bus; local 52 driver D("Driver", clock, bus, control, out); 53 ts_buf B("Buffer", out, control, bus); 54 display DISP("BusDisplay", bus);
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/gem5/src/systemc/tests/tlm/bus/ |
H A D | bus.cpp | 60 SimpleBusAT<7, 7> bus("bus"); 62 initiator1.socket(bus.target_socket[0]); 63 initiator2.socket(bus.target_socket[1]); 64 initiator3.socket(bus.target_socket[2]); 65 initiator4.socket(bus.target_socket[3]); 66 initiator5.socket(bus.target_socket[4]); 67 initiator6.socket(bus.target_socket[5]); 68 initiator7.socket(bus.target_socket[6]); 69 bus [all...] |
/gem5/src/systemc/tests/tlm/bus_dmi/ |
H A D | bus_dmi.cpp | 59 SimpleBusLT<7, 7> bus("bus"); 61 initiator1.socket(bus.target_socket[0]); 62 initiator2.socket(bus.target_socket[1]); 63 initiator3.socket(bus.target_socket[2]); 64 initiator4.socket(bus.target_socket[3]); 65 initiator5.socket(bus.target_socket[4]); 66 initiator6.socket(bus.target_socket[5]); 67 initiator7.socket(bus.target_socket[6]); 68 bus [all...] |
/gem5/src/dev/alpha/ |
H A D | Tsunami.py | 105 # Attach I/O devices to specified bus object. Can't do this 106 # earlier, since the bus object itself is typically defined at the 108 def attachIO(self, bus): 109 self.cchip.pio = bus.master 110 self.pchip.pio = bus.master 111 self.fake_sm_chip.pio = bus.master 112 self.fake_uart1.pio = bus.master 113 self.fake_uart2.pio = bus.master 114 self.fake_uart3.pio = bus.master 115 self.fake_uart4.pio = bus [all...] |
/gem5/src/systemc/tests/tlm/static_extensions/ext2gp2ext/ |
H A D | ext2gp2ext.cpp | 32 SimpleBusLT<1,1> bus("bus"); 37 bridge1.initiator_socket(bus.target_socket[0]); 38 bus.initiator_socket[0](bridge2.target_socket);
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/gem5/src/dev/x86/ |
H A D | Pc.py | 78 def attachIO(self, bus, dma_ports = []): 79 self.south_bridge.attachIO(bus, dma_ports) 80 self.i_dont_exist1.pio = bus.master 81 self.i_dont_exist2.pio = bus.master 82 self.behind_pci.pio = bus.master 83 self.com_1.pio = bus.master 84 self.fake_com_2.pio = bus.master 85 self.fake_com_3.pio = bus.master 86 self.fake_com_4.pio = bus.master 87 self.fake_floppy.pio = bus [all...] |
H A D | SouthBridge.py | 88 def attachIO(self, bus, dma_ports): 101 # Connect to the bus 102 self.cmos.pio = bus.master 103 self.dma1.pio = bus.master 104 self.ide.pio = bus.master 106 self.ide.dma = bus.slave 107 self.keyboard.pio = bus.master 108 self.pic1.pio = bus.master 109 self.pic2.pio = bus.master 110 self.pit.pio = bus [all...] |
/gem5/src/dev/sparc/ |
H A D | T1000.py | 116 def attachOnChipIO(self, bus): 117 self.iob.pio = bus.master 118 self.htod.pio = bus.master 121 # Attach I/O devices to specified bus object. Can't do this 122 # earlier, since the bus object itself is typically defined at the 124 def attachIO(self, bus): 127 self.fake_clk.pio = bus.master 128 self.fake_membnks.pio = bus.master 129 self.fake_l2_1.pio = bus.master 130 self.fake_l2_2.pio = bus [all...] |
H A D | t1000.hh | 86 * Calculate the configuration address given a bus/dev/func. 88 virtual Addr calcPciConfigAddr(int bus, int dev, int func); 91 * Calculate the address for an IO location on the PCI bus. 96 * Calculate the address for a memory location on the PCI bus.
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/gem5/src/dev/pci/ |
H A D | types.hh | 49 : bus(_bus), dev(_dev), func(_func) {} 55 uint8_t bus; member in struct:PciBusAddr 61 return (bus << 16) | (dev << 8) | func;
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H A D | PciHost.py | 67 def pciFdtAddr(self, bus=0, device=0, function=0, register=0, space=0, 70 busf = bus & 0xff 79 if busf != bus or \
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H A D | host.cc | 65 bus_addr.bus, bus_addr.dev, bus_addr.func); 68 "%02x:%02x.%i: PCI bus ID collision\n", 69 bus_addr.bus, bus_addr.dev, bus_addr.func); 100 host.name(), busAddr.bus, busAddr.dev, busAddr.func); 142 dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func, 165 dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func, 172 dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func);
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/gem5/src/systemc/tests/systemc/misc/v1.0/resolved_sig/ |
H A D | resolved_sig.cpp | 54 sc_out_rv<8> bus; local 71 bus( BUS ); 88 sc_inout_rv<8> bus; local 107 bus( BUS ); 132 cout << "; reading from bus=" << bus.read() << endl; 135 cout << "datawidth writing to bus: " << lv << endl; 136 bus.write( lv ); 161 cout << "writing to bus: " << lv << flush; 162 bus [all...] |
/gem5/configs/learning_gem5/part1/ |
H A D | caches.py | 65 def connectBus(self, bus): 66 """Connect this cache to a memory-side bus""" 67 self.mem_side = bus.slave 132 def connectCPUSideBus(self, bus): 133 self.cpu_side = bus.master 135 def connectMemSideBus(self, bus): 136 self.mem_side = bus.slave
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/gem5/src/dev/mips/ |
H A D | Malta.py | 60 # Attach I/O devices to specified bus object. Can't do this 61 # earlier, since the bus object itself is typically defined at the 63 def attachIO(self, bus): 64 self.cchip.pio = bus.master 65 self.io.pio = bus.master 66 self.uart.pio = bus.master
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/gem5/ext/sst/tests/ |
H A D | test6_arm_4c.py | 102 bus = sst.Component("membus", "memHierarchy.Bus") variable 103 bus.addParams({ 120 link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 131 link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 146 link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 148 link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 150 link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 152 link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 167 link.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat))
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/gem5/tests/gem5/cpu_tests/ |
H A D | run.py | 46 def connectBus(self, bus): 47 """Connect this cache to a memory-side bus""" 48 self.mem_side = bus.slave 87 def connectCPUSideBus(self, bus): 88 self.cpu_side = bus.master 90 def connectMemSideBus(self, bus): 91 self.mem_side = bus.slave
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/gem5/src/dev/arm/ |
H A D | pci_host.cc | 57 addr.bus, addr.dev, addr.func);
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H A D | RealView.py | 303 node.appendCompatible("arm,vexpress,config-bus") 336 node.appendCompatible("arm,vexpress,config-bus") 553 def _attach_device(self, device, bus, dma_ports=None): 555 device.pio = bus.master 558 device.dma = bus.slave 583 def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 584 self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 668 def attachOnChipIO(self, bus, bridge): 669 self.gic.pio = bus.master 670 self.l2x0_fake.pio = bus [all...] |
/gem5/src/cpu/testers/traffic_gen/ |
H A D | BaseTrafficGen.py | 114 def connectCachedPorts(self, bus): 117 exec('self.%s = bus.slave' % p) 119 self.port = bus.slave
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