14486Sbinkertn@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Gabe Black 284486Sbinkertn@umich.edu 293630SN/Afrom m5.params import * 303630SN/Afrom m5.proxy import * 3113665Sandreas.sandberg@arm.com 3213665Sandreas.sandberg@arm.comfrom m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 3313665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 3413665Sandreas.sandberg@arm.comfrom m5.objects.Terminal import Terminal 3513665Sandreas.sandberg@arm.comfrom m5.objects.Uart import Uart8250 363630SN/A 373898SN/A 383898SN/Aclass MmDisk(BasicPioDevice): 393898SN/A type = 'MmDisk' 409338SAndreas.Sandberg@arm.com cxx_header = "dev/sparc/mm_disk.hh" 413898SN/A image = Param.DiskImage("Disk Image") 423898SN/A pio_addr = 0x1F40000000 433898SN/A 443914SN/Aclass DumbTOD(BasicPioDevice): 453914SN/A type = 'DumbTOD' 469338SAndreas.Sandberg@arm.com cxx_header = "dev/sparc/dtod.hh" 473914SN/A time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 483914SN/A pio_addr = 0xfff0c1fff8 493914SN/A 504104SN/Aclass Iob(PioDevice): 514104SN/A type = 'Iob' 529338SAndreas.Sandberg@arm.com cxx_header = "dev/sparc/iob.hh" 538742Sgblack@eecs.umich.edu platform = Param.Platform(Parent.any, "Platform this device is part of.") 549162Sandreas.hansson@arm.com pio_latency = Param.Latency('1ns', "Programed IO latency") 554104SN/A 563914SN/A 573630SN/Aclass T1000(Platform): 583630SN/A type = 'T1000' 599338SAndreas.Sandberg@arm.com cxx_header = "dev/sparc/t1000.hh" 603630SN/A system = Param.System(Parent.any, "system") 613630SN/A 624007SN/A fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 634007SN/A #warn_access="Accessing Clock Unit -- Unimplemented!") 643630SN/A 653814SN/A fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 664007SN/A ret_data64=0x0000000000000000, update_data=False) 674007SN/A #warn_access="Accessing Memory Banks -- Unimplemented!") 683814SN/A 694007SN/A fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 704007SN/A #warn_access="Accessing JBI -- Unimplemented!") 713814SN/A 723814SN/A fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 734007SN/A ret_data64=0x0000000000000001, update_data=True) 744007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 753814SN/A 763814SN/A fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 774007SN/A ret_data64=0x0000000000000001, update_data=True) 784007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 793814SN/A 803814SN/A fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 814007SN/A ret_data64=0x0000000000000001, update_data=True) 824007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 833814SN/A 843814SN/A fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 854007SN/A ret_data64=0x0000000000000001, update_data=True) 864007SN/A #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 873814SN/A 883825SN/A fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 894007SN/A ret_data64=0x0000000000000000, update_data=True) 904007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 913825SN/A 923825SN/A fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 934007SN/A ret_data64=0x0000000000000000, update_data=True) 944007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 953825SN/A 963825SN/A fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 974007SN/A ret_data64=0x0000000000000000, update_data=True) 984007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 993825SN/A 1003825SN/A fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 1014007SN/A ret_data64=0x0000000000000000, update_data=True) 1024007SN/A #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 1033825SN/A 1044007SN/A fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 1054007SN/A #warn_access="Accessing SSI -- Unimplemented!") 1063814SN/A 1075478Snate@binkert.org hterm = Terminal() 1083814SN/A hvuart = Uart8250(pio_addr=0xfff0c2c000) 1093914SN/A htod = DumbTOD() 1103914SN/A 1115478Snate@binkert.org pterm = Terminal() 1123814SN/A puart0 = Uart8250(pio_addr=0x1f10000000) 1133630SN/A 1144104SN/A iob = Iob() 1154104SN/A # Attach I/O devices that are on chip 1164104SN/A def attachOnChipIO(self, bus): 1178847Sandreas.hansson@arm.com self.iob.pio = bus.master 1188847Sandreas.hansson@arm.com self.htod.pio = bus.master 1194104SN/A 1204104SN/A 1213630SN/A # Attach I/O devices to specified bus object. Can't do this 1223630SN/A # earlier, since the bus object itself is typically defined at the 1233630SN/A # System level. 1243630SN/A def attachIO(self, bus): 12512274Sgabeblack@google.com self.hvuart.device = self.hterm 12612274Sgabeblack@google.com self.puart0.device = self.pterm 1278847Sandreas.hansson@arm.com self.fake_clk.pio = bus.master 1288847Sandreas.hansson@arm.com self.fake_membnks.pio = bus.master 1298847Sandreas.hansson@arm.com self.fake_l2_1.pio = bus.master 1308847Sandreas.hansson@arm.com self.fake_l2_2.pio = bus.master 1318847Sandreas.hansson@arm.com self.fake_l2_3.pio = bus.master 1328847Sandreas.hansson@arm.com self.fake_l2_4.pio = bus.master 1338847Sandreas.hansson@arm.com self.fake_l2esr_1.pio = bus.master 1348847Sandreas.hansson@arm.com self.fake_l2esr_2.pio = bus.master 1358847Sandreas.hansson@arm.com self.fake_l2esr_3.pio = bus.master 1368847Sandreas.hansson@arm.com self.fake_l2esr_4.pio = bus.master 1378847Sandreas.hansson@arm.com self.fake_ssi.pio = bus.master 1388847Sandreas.hansson@arm.com self.fake_jbi.pio = bus.master 1398847Sandreas.hansson@arm.com self.puart0.pio = bus.master 1408847Sandreas.hansson@arm.com self.hvuart.pio = bus.master 141