1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31
32from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
33from m5.objects.Platform import Platform
34from m5.objects.Terminal import Terminal
35from m5.objects.Uart import Uart8250
36
37
38class MmDisk(BasicPioDevice):
39    type = 'MmDisk'
40    cxx_header = "dev/sparc/mm_disk.hh"
41    image = Param.DiskImage("Disk Image")
42    pio_addr = 0x1F40000000
43
44class DumbTOD(BasicPioDevice):
45    type = 'DumbTOD'
46    cxx_header = "dev/sparc/dtod.hh"
47    time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
48    pio_addr = 0xfff0c1fff8
49
50class Iob(PioDevice):
51    type = 'Iob'
52    cxx_header = "dev/sparc/iob.hh"
53    platform = Param.Platform(Parent.any, "Platform this device is part of.")
54    pio_latency = Param.Latency('1ns', "Programed IO latency")
55
56
57class T1000(Platform):
58    type = 'T1000'
59    cxx_header = "dev/sparc/t1000.hh"
60    system = Param.System(Parent.any, "system")
61
62    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
63            #warn_access="Accessing Clock Unit -- Unimplemented!")
64
65    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
66            ret_data64=0x0000000000000000, update_data=False)
67            #warn_access="Accessing Memory Banks -- Unimplemented!")
68
69    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
70            #warn_access="Accessing JBI -- Unimplemented!")
71
72    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
73            ret_data64=0x0000000000000001, update_data=True)
74            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
75
76    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
77            ret_data64=0x0000000000000001, update_data=True)
78            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
79
80    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
81            ret_data64=0x0000000000000001, update_data=True)
82            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
83
84    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
85            ret_data64=0x0000000000000001, update_data=True)
86            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
87
88    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
89            ret_data64=0x0000000000000000, update_data=True)
90            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
91
92    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
93            ret_data64=0x0000000000000000, update_data=True)
94            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
95
96    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
97            ret_data64=0x0000000000000000, update_data=True)
98            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
99
100    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
101            ret_data64=0x0000000000000000, update_data=True)
102            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
103
104    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
105            #warn_access="Accessing SSI -- Unimplemented!")
106
107    hterm = Terminal()
108    hvuart = Uart8250(pio_addr=0xfff0c2c000)
109    htod = DumbTOD()
110
111    pterm = Terminal()
112    puart0 = Uart8250(pio_addr=0x1f10000000)
113
114    iob = Iob()
115    # Attach I/O devices that are on chip
116    def attachOnChipIO(self, bus):
117        self.iob.pio = bus.master
118        self.htod.pio = bus.master
119
120
121    # Attach I/O devices to specified bus object.  Can't do this
122    # earlier, since the bus object itself is typically defined at the
123    # System level.
124    def attachIO(self, bus):
125        self.hvuart.device = self.hterm
126        self.puart0.device = self.pterm
127        self.fake_clk.pio = bus.master
128        self.fake_membnks.pio = bus.master
129        self.fake_l2_1.pio = bus.master
130        self.fake_l2_2.pio = bus.master
131        self.fake_l2_3.pio = bus.master
132        self.fake_l2_4.pio = bus.master
133        self.fake_l2esr_1.pio = bus.master
134        self.fake_l2esr_2.pio = bus.master
135        self.fake_l2esr_3.pio = bus.master
136        self.fake_l2esr_4.pio = bus.master
137        self.fake_ssi.pio = bus.master
138        self.fake_jbi.pio = bus.master
139        self.puart0.pio = bus.master
140        self.hvuart.pio = bus.master
141