111618SCurtis.Dunham@arm.com# Copyright (c) 2015-2016 ARM Limited 210780SCurtis.Dunham@arm.com# All rights reserved. 310780SCurtis.Dunham@arm.com# 410780SCurtis.Dunham@arm.com# The license below extends only to copyright in the software and shall 510780SCurtis.Dunham@arm.com# not be construed as granting a license to any other intellectual 610780SCurtis.Dunham@arm.com# property including but not limited to intellectual property relating 710780SCurtis.Dunham@arm.com# to a hardware implementation of the functionality of the software 810780SCurtis.Dunham@arm.com# licensed hereunder. You may use the software subject to the license 910780SCurtis.Dunham@arm.com# terms below provided that you ensure that this notice is replicated 1010780SCurtis.Dunham@arm.com# unmodified and in its entirety in all distributions of the software, 1110780SCurtis.Dunham@arm.com# modified or unmodified, in source code or in binary form. 1210780SCurtis.Dunham@arm.com# 1310780SCurtis.Dunham@arm.com# Redistribution and use in source and binary forms, with or without 1410780SCurtis.Dunham@arm.com# modification, are permitted provided that the following conditions are 1510780SCurtis.Dunham@arm.com# met: redistributions of source code must retain the above copyright 1610780SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer; 1710780SCurtis.Dunham@arm.com# redistributions in binary form must reproduce the above copyright 1810780SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer in the 1910780SCurtis.Dunham@arm.com# documentation and/or other materials provided with the distribution; 2010780SCurtis.Dunham@arm.com# neither the name of the copyright holders nor the names of its 2110780SCurtis.Dunham@arm.com# contributors may be used to endorse or promote products derived from 2210780SCurtis.Dunham@arm.com# this software without specific prior written permission. 2310780SCurtis.Dunham@arm.com# 2410780SCurtis.Dunham@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510780SCurtis.Dunham@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610780SCurtis.Dunham@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710780SCurtis.Dunham@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810780SCurtis.Dunham@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910780SCurtis.Dunham@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010780SCurtis.Dunham@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110780SCurtis.Dunham@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210780SCurtis.Dunham@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310780SCurtis.Dunham@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410780SCurtis.Dunham@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510780SCurtis.Dunham@arm.com# 3610780SCurtis.Dunham@arm.com# Authors: Curtis Dunham 3710780SCurtis.Dunham@arm.com 3810780SCurtis.Dunham@arm.comimport sst 3910780SCurtis.Dunham@arm.comimport sys 4010780SCurtis.Dunham@arm.comimport os 4110780SCurtis.Dunham@arm.com 4210780SCurtis.Dunham@arm.comlat="1 ns" 4310780SCurtis.Dunham@arm.combuslat="2 ns" 4410780SCurtis.Dunham@arm.comclockRate = "1GHz" 4510780SCurtis.Dunham@arm.com 4610780SCurtis.Dunham@arm.com 4710780SCurtis.Dunham@arm.comdef getenv(name): 4810780SCurtis.Dunham@arm.com res = "" 4910780SCurtis.Dunham@arm.com try: 5010780SCurtis.Dunham@arm.com res = os.environ[name] 5110780SCurtis.Dunham@arm.com except KeyError: 5210780SCurtis.Dunham@arm.com pass 5310780SCurtis.Dunham@arm.com return res 5410780SCurtis.Dunham@arm.com 5511617SCurtis.Dunham@arm.comdef debug(d): 5611617SCurtis.Dunham@arm.com try: 5711617SCurtis.Dunham@arm.com r = int(getenv(d)) 5811617SCurtis.Dunham@arm.com except ValueError: 5911617SCurtis.Dunham@arm.com return 0 6011617SCurtis.Dunham@arm.com return r 6111617SCurtis.Dunham@arm.com 6210780SCurtis.Dunham@arm.combaseCacheParams = ({ 6311617SCurtis.Dunham@arm.com "debug" :debug("DEBUG"), 6410780SCurtis.Dunham@arm.com "debug_level" : 6, 6510780SCurtis.Dunham@arm.com "coherence_protocol" : "MSI", 6610780SCurtis.Dunham@arm.com "replacement_policy" : "LRU", 6710780SCurtis.Dunham@arm.com "cache_line_size" : 64, 6811617SCurtis.Dunham@arm.com "cache_frequency" : clockRate 6910780SCurtis.Dunham@arm.com }) 7010780SCurtis.Dunham@arm.com 7110780SCurtis.Dunham@arm.coml1CacheParams = ({ 7211617SCurtis.Dunham@arm.com "debug" : debug("DEBUG"), 7310780SCurtis.Dunham@arm.com "debug_level" : 6, 7410780SCurtis.Dunham@arm.com "L1" : 1, 7510780SCurtis.Dunham@arm.com "cache_size" : "64 KB", 7610780SCurtis.Dunham@arm.com "associativity" : 4, 7710780SCurtis.Dunham@arm.com "access_latency_cycles" : 2, 7810780SCurtis.Dunham@arm.com "low_network_links" : 1 7910780SCurtis.Dunham@arm.com }) 8010780SCurtis.Dunham@arm.com 8110780SCurtis.Dunham@arm.coml2CacheParams = ({ 8211617SCurtis.Dunham@arm.com "debug" : debug("DEBUG"), 8310780SCurtis.Dunham@arm.com "debug_level" : 6, 8410780SCurtis.Dunham@arm.com "L1" : 0, 8510780SCurtis.Dunham@arm.com "cache_size" : "256 KB", 8610780SCurtis.Dunham@arm.com "associativity" : 8, 8710780SCurtis.Dunham@arm.com "access_latency_cycles" : 8, 8810780SCurtis.Dunham@arm.com "high_network_links" : 1, 8910780SCurtis.Dunham@arm.com "mshr_num_entries" : 4096, 9010780SCurtis.Dunham@arm.com "low_network_links" : 1 9110780SCurtis.Dunham@arm.com }) 9210780SCurtis.Dunham@arm.com 9310780SCurtis.Dunham@arm.com 9410780SCurtis.Dunham@arm.comGEM5 = sst.Component("system", "gem5.gem5") 9510780SCurtis.Dunham@arm.comGEM5.addParams({ 9611617SCurtis.Dunham@arm.com "comp_debug" : debug("GEM5_DEBUG"), 9711617SCurtis.Dunham@arm.com "gem5DebugFlags" : debug("M5_DEBUG"), 9810780SCurtis.Dunham@arm.com "frequency" : clockRate, 9911314SCurtis.Dunham@arm.com "cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst" 10010780SCurtis.Dunham@arm.com }) 10110780SCurtis.Dunham@arm.com 10210780SCurtis.Dunham@arm.combus = sst.Component("membus", "memHierarchy.Bus") 10310780SCurtis.Dunham@arm.combus.addParams({ 10410780SCurtis.Dunham@arm.com "bus_frequency": "2GHz", 10511617SCurtis.Dunham@arm.com "debug" : debug("DEBUG"), 10610780SCurtis.Dunham@arm.com "debug_level" : 8 10710780SCurtis.Dunham@arm.com }) 10810780SCurtis.Dunham@arm.com 10910780SCurtis.Dunham@arm.comdef buildL1(name, m5, connector): 11010780SCurtis.Dunham@arm.com cache = sst.Component(name, "memHierarchy.Cache") 11110780SCurtis.Dunham@arm.com cache.addParams(baseCacheParams) 11210780SCurtis.Dunham@arm.com cache.addParams(l1CacheParams) 11310780SCurtis.Dunham@arm.com link = sst.Link("cpu_%s_link"%name) 11410780SCurtis.Dunham@arm.com link.connect((m5, connector, lat), (cache, "high_network_0", lat)) 11510780SCurtis.Dunham@arm.com return cache 11610780SCurtis.Dunham@arm.com 11710780SCurtis.Dunham@arm.comSysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port") 11810780SCurtis.Dunham@arm.combus_port = 0 11910780SCurtis.Dunham@arm.comlink = sst.Link("sysbus_bus_link") 12010780SCurtis.Dunham@arm.comlink.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 12110780SCurtis.Dunham@arm.com 12210780SCurtis.Dunham@arm.combus_port = bus_port + 1 12310780SCurtis.Dunham@arm.comioCache = buildL1("ioCache", GEM5, "system.iocache.port") 12410780SCurtis.Dunham@arm.comioCache.addParams({ 12510780SCurtis.Dunham@arm.com "debug" : 0, 12610780SCurtis.Dunham@arm.com "debug_level" : 6, 12710780SCurtis.Dunham@arm.com "cache_size" : "16 KB", 12810780SCurtis.Dunham@arm.com "associativity" : 4 12910780SCurtis.Dunham@arm.com }) 13010780SCurtis.Dunham@arm.comlink = sst.Link("ioCache_bus_link") 13110780SCurtis.Dunham@arm.comlink.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 13210780SCurtis.Dunham@arm.com 13310780SCurtis.Dunham@arm.comdef buildCPU(m5, num): 13410780SCurtis.Dunham@arm.com l1iCache = buildL1("cpu%u.l1iCache" % num, m5, "system.cpu%u.icache.port" % num) 13510780SCurtis.Dunham@arm.com l1dCache = buildL1("cpu%u.l1dCache" % num, m5, "system.cpu%u.dcache.port" % num) 13610780SCurtis.Dunham@arm.com itlbCache = buildL1("cpu%u.itlbCache" % num, m5, "system.cpu%u.itb_walker_cache.port" % num) 13710780SCurtis.Dunham@arm.com dtlbCache = buildL1("cpu%u.dtlbCache" % num, m5, "system.cpu%u.dtb_walker_cache.port" % num) 13810780SCurtis.Dunham@arm.com l1dCache.addParams({ 13910780SCurtis.Dunham@arm.com "debug" : 0, 14010780SCurtis.Dunham@arm.com "debug_level" : 10, 14110780SCurtis.Dunham@arm.com "snoop_l1_invalidations" : 1 14210780SCurtis.Dunham@arm.com }) 14310780SCurtis.Dunham@arm.com 14410780SCurtis.Dunham@arm.com global bus_port 14510780SCurtis.Dunham@arm.com link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1 14610780SCurtis.Dunham@arm.com link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 14710780SCurtis.Dunham@arm.com link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1 14810780SCurtis.Dunham@arm.com link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 14910780SCurtis.Dunham@arm.com link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1 15010780SCurtis.Dunham@arm.com link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 15110780SCurtis.Dunham@arm.com link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1 15210780SCurtis.Dunham@arm.com link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat)) 15310780SCurtis.Dunham@arm.com 15410780SCurtis.Dunham@arm.combuildCPU(GEM5, 0) 15510780SCurtis.Dunham@arm.combuildCPU(GEM5, 1) 15610780SCurtis.Dunham@arm.combuildCPU(GEM5, 2) 15710780SCurtis.Dunham@arm.combuildCPU(GEM5, 3) 15810780SCurtis.Dunham@arm.com 15910780SCurtis.Dunham@arm.coml2cache = sst.Component("l2cache", "memHierarchy.Cache") 16010780SCurtis.Dunham@arm.coml2cache.addParams(baseCacheParams) 16110780SCurtis.Dunham@arm.coml2cache.addParams(l2CacheParams) 16210780SCurtis.Dunham@arm.coml2cache.addParams({ 16311617SCurtis.Dunham@arm.com "network_address" : "2" 16410780SCurtis.Dunham@arm.com}) 16510780SCurtis.Dunham@arm.com 16610780SCurtis.Dunham@arm.comlink = sst.Link("l2cache_bus_link") 16710780SCurtis.Dunham@arm.comlink.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat)) 16810780SCurtis.Dunham@arm.com 16910780SCurtis.Dunham@arm.commemory = sst.Component("memory", "memHierarchy.MemController") 17010780SCurtis.Dunham@arm.commemory.addParams({ 17110780SCurtis.Dunham@arm.com "request_width" : 64, 17210780SCurtis.Dunham@arm.com "coherence_protocol" : "MSI", 17310780SCurtis.Dunham@arm.com "access_time" : "25 ns", 17411647SCurtis.Dunham@arm.com "backend.mem_size" : "256MiB", 17510780SCurtis.Dunham@arm.com "clock" : "2GHz", 17611617SCurtis.Dunham@arm.com "debug" : debug("DEBUG"), 17710780SCurtis.Dunham@arm.com "range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller. 17810780SCurtis.Dunham@arm.com }) 17910780SCurtis.Dunham@arm.com 18010780SCurtis.Dunham@arm.comcomp_chiprtr = sst.Component("chiprtr", "merlin.hr_router") 18110780SCurtis.Dunham@arm.comcomp_chiprtr.addParams({ 18210780SCurtis.Dunham@arm.com "xbar_bw" : "16GB/s", 18310780SCurtis.Dunham@arm.com "link_bw" : "16GB/s", 18410780SCurtis.Dunham@arm.com "input_buf_size" : "1KB", 18510780SCurtis.Dunham@arm.com "num_ports" : "3", 18610780SCurtis.Dunham@arm.com "flit_size" : "72B", 18710780SCurtis.Dunham@arm.com "output_buf_size" : "1KB", 18810780SCurtis.Dunham@arm.com "id" : "0", 18910780SCurtis.Dunham@arm.com "topology" : "merlin.singlerouter" 19010780SCurtis.Dunham@arm.com}) 19110780SCurtis.Dunham@arm.comcomp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController") 19210780SCurtis.Dunham@arm.comcomp_dirctrl.addParams({ 19310780SCurtis.Dunham@arm.com "coherence_protocol" : "MSI", 19410780SCurtis.Dunham@arm.com "network_address" : "1", 19510780SCurtis.Dunham@arm.com "entry_cache_size" : "16384", 19610780SCurtis.Dunham@arm.com "network_bw" : "1GB/s", 19710780SCurtis.Dunham@arm.com "addr_range_start" : 2 * (1024 ** 3), 19810780SCurtis.Dunham@arm.com "addr_range_end" : 2 * (1024 ** 3) + 256 * (1024 ** 2) 19910780SCurtis.Dunham@arm.com}) 20010780SCurtis.Dunham@arm.com 20110780SCurtis.Dunham@arm.comsst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns")) 20210780SCurtis.Dunham@arm.comsst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns")) 20310780SCurtis.Dunham@arm.comsst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat)) 20410780SCurtis.Dunham@arm.comsst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns")) 205