1# Copyright (c) 2015-2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Curtis Dunham
37
38import sst
39import sys
40import os
41
42lat="1 ns"
43buslat="2 ns"
44clockRate = "1GHz"
45
46
47def getenv(name):
48    res = ""
49    try:
50        res = os.environ[name]
51    except KeyError:
52        pass
53    return res
54
55def debug(d):
56    try:
57        r = int(getenv(d))
58    except ValueError:
59        return 0
60    return r
61
62baseCacheParams = ({
63    "debug" :debug("DEBUG"),
64    "debug_level" : 6,
65    "coherence_protocol" : "MSI",
66    "replacement_policy" : "LRU",
67    "cache_line_size" : 64,
68    "cache_frequency" : clockRate
69    })
70
71l1CacheParams = ({
72    "debug" : debug("DEBUG"),
73    "debug_level" : 6,
74    "L1" : 1,
75    "cache_size" : "64 KB",
76    "associativity" : 4,
77    "access_latency_cycles" : 2,
78    "low_network_links" : 1
79    })
80
81l2CacheParams = ({
82    "debug" : debug("DEBUG"),
83    "debug_level" : 6,
84    "L1" : 0,
85    "cache_size" : "256 KB",
86    "associativity" : 8,
87    "access_latency_cycles" : 8,
88    "high_network_links" : 1,
89    "mshr_num_entries" : 4096,
90    "low_network_links" : 1
91    })
92
93
94GEM5 = sst.Component("system", "gem5.gem5")
95GEM5.addParams({
96    "comp_debug" : debug("GEM5_DEBUG"),
97    "gem5DebugFlags" : debug("M5_DEBUG"),
98    "frequency" : clockRate,
99    "cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst"
100    })
101
102bus = sst.Component("membus", "memHierarchy.Bus")
103bus.addParams({
104    "bus_frequency": "2GHz",
105    "debug" : debug("DEBUG"),
106    "debug_level" : 8
107    })
108
109def buildL1(name, m5, connector):
110    cache = sst.Component(name, "memHierarchy.Cache")
111    cache.addParams(baseCacheParams)
112    cache.addParams(l1CacheParams)
113    link = sst.Link("cpu_%s_link"%name)
114    link.connect((m5, connector, lat), (cache, "high_network_0", lat))
115    return cache
116
117SysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port")
118bus_port = 0
119link = sst.Link("sysbus_bus_link")
120link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
121
122bus_port = bus_port + 1
123ioCache = buildL1("ioCache", GEM5, "system.iocache.port")
124ioCache.addParams({
125    "debug" : 0,
126    "debug_level" : 6,
127    "cache_size" : "16 KB",
128    "associativity" : 4
129    })
130link = sst.Link("ioCache_bus_link")
131link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
132
133def buildCPU(m5, num):
134    l1iCache = buildL1("cpu%u.l1iCache" % num, m5, "system.cpu%u.icache.port" % num)
135    l1dCache = buildL1("cpu%u.l1dCache" % num, m5, "system.cpu%u.dcache.port" % num)
136    itlbCache = buildL1("cpu%u.itlbCache" % num, m5, "system.cpu%u.itb_walker_cache.port" % num)
137    dtlbCache = buildL1("cpu%u.dtlbCache" % num, m5, "system.cpu%u.dtb_walker_cache.port" % num)
138    l1dCache.addParams({
139        "debug" : 0,
140        "debug_level" : 10,
141        "snoop_l1_invalidations" : 1
142    })
143
144    global bus_port
145    link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1
146    link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
147    link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1
148    link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
149    link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1
150    link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
151    link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1
152    link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
153
154buildCPU(GEM5, 0)
155buildCPU(GEM5, 1)
156buildCPU(GEM5, 2)
157buildCPU(GEM5, 3)
158
159l2cache = sst.Component("l2cache", "memHierarchy.Cache")
160l2cache.addParams(baseCacheParams)
161l2cache.addParams(l2CacheParams)
162l2cache.addParams({
163      "network_address" : "2"
164})
165
166link = sst.Link("l2cache_bus_link")
167link.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat))
168
169memory = sst.Component("memory", "memHierarchy.MemController")
170memory.addParams({
171    "request_width" : 64,
172    "coherence_protocol" : "MSI",
173    "access_time" : "25 ns",
174    "backend.mem_size" : "256MiB",
175    "clock" : "2GHz",
176    "debug" : debug("DEBUG"),
177    "range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
178    })
179
180comp_chiprtr = sst.Component("chiprtr", "merlin.hr_router")
181comp_chiprtr.addParams({
182      "xbar_bw" : "16GB/s",
183      "link_bw" : "16GB/s",
184      "input_buf_size" : "1KB",
185      "num_ports" : "3",
186      "flit_size" : "72B",
187      "output_buf_size" : "1KB",
188      "id" : "0",
189      "topology" : "merlin.singlerouter"
190})
191comp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController")
192comp_dirctrl.addParams({
193      "coherence_protocol" : "MSI",
194      "network_address" : "1",
195      "entry_cache_size" : "16384",
196      "network_bw" : "1GB/s",
197      "addr_range_start" : 2 * (1024 ** 3),
198      "addr_range_end" : 2 * (1024 ** 3) + 256 * (1024 ** 2)
199})
200
201sst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns"))
202sst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns"))
203sst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat))
204sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))
205