Lines Matching refs:bus
78 def attachIO(self, bus, dma_ports = []):
79 self.south_bridge.attachIO(bus, dma_ports)
80 self.i_dont_exist1.pio = bus.master
81 self.i_dont_exist2.pio = bus.master
82 self.behind_pci.pio = bus.master
83 self.com_1.pio = bus.master
84 self.fake_com_2.pio = bus.master
85 self.fake_com_3.pio = bus.master
86 self.fake_com_4.pio = bus.master
87 self.fake_floppy.pio = bus.master
88 self.pci_host.pio = bus.default