Searched hist:2008 (Results 376 - 400 of 494) sorted by relevance

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/gem5/src/cpu/o3/
H A Dlsq.hhdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
H A Dlsq_impl.hhdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5557:03c186e416aa Fri Sep 26 10:44:00 EDT 2008 Kevin Lim <ktlim@umich.edu> O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
H A DSConscriptdiff 5597:e2983d751be4 Thu Oct 09 03:10:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 IMPL class so it isn't split out by ISA.
H A Dmem_dep_unit.hhdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
/gem5/src/cpu/simple/
H A Datomic.hhdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5496:6899b894166f Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
diff 5487:f0ac4112e128 Wed Jun 18 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> AtomicSimpleCPU: Separate data stalls from instruction stalls.
Separate simulation of icache stalls and dat stalls.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
diff 5315:30997e988446 Wed Jan 02 16:46:00 EST 2008 Steve Reinhardt <stever@gmail.com> Additional comments and helper functions for PrintReq.
/gem5/src/cpu/
H A Dbase.hhdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function.
diff 5645:0d35ed236aa1 Sat Oct 11 19:13:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Add a getInterruptController function
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
H A Dthread_context.hhdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code.
diff 5592:6e0569faeeef Thu Oct 09 03:06:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Fix where setMicroPC was being called instead of setNextMicroPC.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5497:89a6483d7047 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make the cached virtPort have a thread context so it can do everything that a newly created one can.
H A Dexec_context.hhdiff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
H A Dintr_control.ccdiff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
/gem5/src/mem/
H A Dpacket.hhdiff 5764:f07df23e1fc8 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> flags: Change naming of functions to be clearer
diff 5745:6b0f8306704b Fri Nov 14 07:55:00 EST 2008 Nathan Binkert <nate@binkert.org> Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out. I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
diff 5735:a88e8e7dec75 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> style: clean up the Packet stuff
diff 5650:d2782c951841 Sun Oct 12 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Create a message port for sending messages as apposed to reading/writing a memory range.
diff 5507:52bcc301b467 Tue Jul 15 14:38:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.
diff 5387:3323952c3bb4 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Delete the Request for a no-response Packet
when the Packet is deleted, since the requester
can't possibly do it.
diff 5386:5614618f4027 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Don't FastAlloc MSHRs since we don't allocate them on the fly.
diff 5319:13cb690ba6d6 Wed Jan 02 18:22:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add ReadRespWithInvalidate to handle multi-level coherence situation
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
diff 5315:30997e988446 Wed Jan 02 16:46:00 EST 2008 Steve Reinhardt <stever@gmail.com> Additional comments and helper functions for PrintReq.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
H A Dbridge.hhdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5386:5614618f4027 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Don't FastAlloc MSHRs since we don't allocate them on the fly.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
H A DSConscriptdiff 5650:d2782c951841 Sun Oct 12 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Create a message port for sending messages as apposed to reading/writing a memory range.
diff 5400:fee00a595efc Thu Apr 10 15:38:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: add comments to SConscript documenting bug workaround
diff 5398:9727ba4600de Tue Apr 08 11:08:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Manually specifying header only directories with Dir() works around the problem
/gem5/src/sim/
H A Dsystem.ccdiff 5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system. To make them match,
here is a little change.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in
SE. Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5530:bbfff6d0c42c Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Get rid of the remnants of the old style parameter configuration stuff.
diff 5512:755fcaf7a4cf Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> RemoteGDB: add an m5 command line option for setting or disabling remote gdb.
H A Dserialize.ccdiff 5739:27c1d1048c65 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> clean: Move some stuff from the hh file to the cc file.
diff 5581:5e1863e9afa2 Thu Oct 02 00:46:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Output: Verify output files are open after opening them.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
H A Dstat_control.ccdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
/gem5/src/python/m5/
H A DSimObject.pydiff 5766:37b74394f2f9 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> SimObject: change naming of vectors so there are the same numbers of digits.
i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100
now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100
diff 5610:0e1e9c186769 Fri Oct 10 01:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> SimObjects: Clean up handling of C++ namespaces.
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5488:c8571e8ce7b6 Wed Jun 18 03:07:00 EDT 2008 Nathan Binkert <nate@binkert.org> imported patch sim_object_params.diff
diff 5467:6d9df90d70d7 Sat Jun 14 23:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: Move various utility classes into a new m5.util package so
they're all in the same place. This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication. Lots of improvements to the utility as well.
diff 5454:4b1261c2af58 Thu Jun 12 01:00:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Params: Allow nested namespaces in cxx_namespace
/gem5/src/cpu/checker/
H A Dcpu.hhdiff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
/gem5/src/mem/cache/
H A Dmshr.ccdiff 5730:dea5fcd1ead0 Mon Nov 10 17:10:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Cache: Refactor packet forwarding a bit.
Makes adding write-through operations easier.
diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
/gem5/src/arch/alpha/freebsd/
H A Dsystem.ccdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
/gem5/src/arch/alpha/
H A DSConscriptdiff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
/gem5/src/arch/x86/isa/microops/
H A Dspecop.isadiff 5449:89b696c8b754 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the disassembly for halt conform with the other microops.
/gem5/src/arch/sparc/
H A Dtypes.hhdiff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code.
/gem5/src/base/
H A Dtime.ccdiff 5546:4ffc3cafba9b Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> Use the proper version of C++ headers
/gem5/src/dev/sparc/
H A Dt1000.ccdiff 5478:ca055528a3b3 Tue Jun 17 23:29:00 EDT 2008 Nathan Binkert <nate@binkert.org> Rename SimConsole to Terminal since it makes more sense
/gem5/configs/common/
H A DCaches.pydiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.

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