1/*
2 * Copyright (c) 2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
44#define __CPU_O3_MEM_DEP_UNIT_HH__
45
46#include <list>
47#include <memory>
48#include <set>
49#include <unordered_map>
50
51#include "base/statistics.hh"
52#include "cpu/inst_seq.hh"
53#include "debug/MemDepUnit.hh"
54
55struct SNHash {
56    size_t operator() (const InstSeqNum &seq_num) const {
57        unsigned a = (unsigned)seq_num;
58        unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
59
60        return hash;
61    }
62};
63
64struct DerivO3CPUParams;
65
66template <class Impl>
67class InstructionQueue;
68
69/**
70 * Memory dependency unit class.  This holds the memory dependence predictor.
71 * As memory operations are issued to the IQ, they are also issued to this
72 * unit, which then looks up the prediction as to what they are dependent
73 * upon.  This unit must be checked prior to a memory operation being able
74 * to issue.  Although this is templated, it's somewhat hard to make a generic
75 * memory dependence unit.  This one is mostly for store sets; it will be
76 * quite limited in what other memory dependence predictions it can also
77 * utilize.  Thus this class should be most likely be rewritten for other
78 * dependence prediction schemes.
79 */
80template <class MemDepPred, class Impl>
81class MemDepUnit
82{
83  protected:
84    std::string _name;
85
86  public:
87    typedef typename Impl::DynInstPtr DynInstPtr;
88    typedef typename Impl::DynInstConstPtr DynInstConstPtr;
89
90    /** Empty constructor. Must call init() prior to using in this case. */
91    MemDepUnit();
92
93    /** Constructs a MemDepUnit with given parameters. */
94    MemDepUnit(DerivO3CPUParams *params);
95
96    /** Frees up any memory allocated. */
97    ~MemDepUnit();
98
99    /** Returns the name of the memory dependence unit. */
100    std::string name() const { return _name; }
101
102    /** Initializes the unit with parameters and a thread id. */
103    void init(DerivO3CPUParams *params, ThreadID tid);
104
105    /** Registers statistics. */
106    void regStats();
107
108    /** Determine if we are drained. */
109    bool isDrained() const;
110
111    /** Perform sanity checks after a drain. */
112    void drainSanityCheck() const;
113
114    /** Takes over from another CPU's thread. */
115    void takeOverFrom();
116
117    /** Sets the pointer to the IQ. */
118    void setIQ(InstructionQueue<Impl> *iq_ptr);
119
120    /** Inserts a memory instruction. */
121    void insert(const DynInstPtr &inst);
122
123    /** Inserts a non-speculative memory instruction. */
124    void insertNonSpec(const DynInstPtr &inst);
125
126    /** Inserts a barrier instruction. */
127    void insertBarrier(const DynInstPtr &barr_inst);
128
129    /** Indicate that an instruction has its registers ready. */
130    void regsReady(const DynInstPtr &inst);
131
132    /** Indicate that a non-speculative instruction is ready. */
133    void nonSpecInstReady(const DynInstPtr &inst);
134
135    /** Reschedules an instruction to be re-executed. */
136    void reschedule(const DynInstPtr &inst);
137
138    /** Replays all instructions that have been rescheduled by moving them to
139     *  the ready list.
140     */
141    void replay();
142
143    /** Completes a memory instruction. */
144    void completed(const DynInstPtr &inst);
145
146    /** Completes a barrier instruction. */
147    void completeBarrier(const DynInstPtr &inst);
148
149    /** Wakes any dependents of a memory instruction. */
150    void wakeDependents(const DynInstPtr &inst);
151
152    /** Squashes all instructions up until a given sequence number for a
153     *  specific thread.
154     */
155    void squash(const InstSeqNum &squashed_num, ThreadID tid);
156
157    /** Indicates an ordering violation between a store and a younger load. */
158    void violation(const DynInstPtr &store_inst,
159                   const DynInstPtr &violating_load);
160
161    /** Issues the given instruction */
162    void issue(const DynInstPtr &inst);
163
164    /** Debugging function to dump the lists of instructions. */
165    void dumpLists();
166
167  private:
168    typedef typename std::list<DynInstPtr>::iterator ListIt;
169
170    class MemDepEntry;
171
172    typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
173
174    /** Memory dependence entries that track memory operations, marking
175     *  when the instruction is ready to execute and what instructions depend
176     *  upon it.
177     */
178    class MemDepEntry {
179      public:
180        /** Constructs a memory dependence entry. */
181        MemDepEntry(const DynInstPtr &new_inst)
182            : inst(new_inst), regsReady(false), memDepReady(false),
183              completed(false), squashed(false)
184        {
185#ifdef DEBUG
186            ++memdep_count;
187
188            DPRINTF(MemDepUnit, "Memory dependency entry created.  "
189                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
190#endif
191        }
192
193        /** Frees any pointers. */
194        ~MemDepEntry()
195        {
196            for (int i = 0; i < dependInsts.size(); ++i) {
197                dependInsts[i] = NULL;
198            }
199#ifdef DEBUG
200            --memdep_count;
201
202            DPRINTF(MemDepUnit, "Memory dependency entry deleted.  "
203                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
204#endif
205        }
206
207        /** Returns the name of the memory dependence entry. */
208        std::string name() const { return "memdepentry"; }
209
210        /** The instruction being tracked. */
211        DynInstPtr inst;
212
213        /** The iterator to the instruction's location inside the list. */
214        ListIt listIt;
215
216        /** A vector of any dependent instructions. */
217        std::vector<MemDepEntryPtr> dependInsts;
218
219        /** If the registers are ready or not. */
220        bool regsReady;
221        /** If all memory dependencies have been satisfied. */
222        bool memDepReady;
223        /** If the instruction is completed. */
224        bool completed;
225        /** If the instruction is squashed. */
226        bool squashed;
227
228        /** For debugging. */
229#ifdef DEBUG
230        static int memdep_count;
231        static int memdep_insert;
232        static int memdep_erase;
233#endif
234    };
235
236    /** Finds the memory dependence entry in the hash map. */
237    inline MemDepEntryPtr &findInHash(const DynInstConstPtr& inst);
238
239    /** Moves an entry to the ready list. */
240    inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
241
242    typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
243
244    typedef typename MemDepHash::iterator MemDepHashIt;
245
246    /** A hash map of all memory dependence entries. */
247    MemDepHash memDepHash;
248
249    /** A list of all instructions in the memory dependence unit. */
250    std::list<DynInstPtr> instList[Impl::MaxThreads];
251
252    /** A list of all instructions that are going to be replayed. */
253    std::list<DynInstPtr> instsToReplay;
254
255    /** The memory dependence predictor.  It is accessed upon new
256     *  instructions being added to the IQ, and responds by telling
257     *  this unit what instruction the newly added instruction is dependent
258     *  upon.
259     */
260    MemDepPred depPred;
261
262    /** Is there an outstanding load barrier that loads must wait on. */
263    bool loadBarrier;
264    /** The sequence number of the load barrier. */
265    InstSeqNum loadBarrierSN;
266    /** Is there an outstanding store barrier that loads must wait on. */
267    bool storeBarrier;
268    /** The sequence number of the store barrier. */
269    InstSeqNum storeBarrierSN;
270
271    /** Pointer to the IQ. */
272    InstructionQueue<Impl> *iqPtr;
273
274    /** The thread id of this memory dependence unit. */
275    int id;
276
277    /** Stat for number of inserted loads. */
278    Stats::Scalar insertedLoads;
279    /** Stat for number of inserted stores. */
280    Stats::Scalar insertedStores;
281    /** Stat for number of conflicting loads that had to wait for a store. */
282    Stats::Scalar conflictingLoads;
283    /** Stat for number of conflicting stores that had to wait for a store. */
284    Stats::Scalar conflictingStores;
285};
286
287#endif // __CPU_O3_MEM_DEP_UNIT_HH__
288