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13892:0182a0601f66 |
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22-Apr-2019 |
Gabe Black <gabeblack@google.com> |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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13883:f44e21d3aaa7 |
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18-Apr-2018 |
David Hashe <david.hashe@amd.com> |
sim-se: add a faux-filesystem
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected.
This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change).
Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode.
Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
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#
13784:1941dc118243 |
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07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary.
Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13644:6180ee72e061 |
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02-Apr-2018 |
Tuan Ta <qtt2@cornell.edu> |
sim,cpu: make exit_group halt all threads in a group
When a thread calls exit_group, in addition to halting the thread itself, it needs to halt all other threads in its group (i.e., threads sharing the same thread group ID). This patch enables threads to do that.
Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03 Reviewed-on: https://gem5-review.googlesource.com/c/9623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12965:8d8a5c770ea8 |
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10-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim: Add System method for MasterID lookup
A new method (lookupMasterId) has been added to the System. A client should use it when querying the System for the MasterID of a particular master. It changes from getMasterId since it is not registering a new MasterID if the master is not found in the master's list.
Change-Id: I701158d22e235085bba9ab91154fbb702cae1467 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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#
12694:157b4b3a9879 |
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02-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim: Remove trailing dot when assigning a master's name
This patch fixes the master's name allocation in the system. The error was occurring when a submaster was not specified in getMasterId: a trailing separation dot was still added to the master's name.
Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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#
12680:91f4d6668b4f |
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04-Apr-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim,cpu,mem,arch: Introduced MasterInfo data structure
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer.
Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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#
12515:e3d1a64d0260 |
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05-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim: Remove _numContexts member in System class
A System object has a _numContexts member variable which represent the number of ThreadContext registered in the System. Since this has to match the size of the ThreadContext vector, this patch removes the manually cached size. This was usually used as a for-loop index, whereas we want to enforce the use of range-based loops whenever possible.
Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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#
12449:2260f4a68210 |
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16-Jan-2018 |
Gabe Black <gabeblack@google.com> |
sim, arch, base: Refactor the base remote GDB class.
Fold the GDBListener class into the main BaseRemoteGDB class, move around a bunch of functions, convert a lot of internal functions to be private, move some functions into the .cc, make some functions non-virtual which didn't really need to be overridden.
Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d Reviewed-on: https://gem5-review.googlesource.com/7422 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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12443:0479f5e6f8bd |
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12-Jan-2018 |
Gabe Black <gabeblack@google.com> |
sim: Simplify registerThreadContext a little bit.
The code in this function was a little convoluted. This change attempts to simplify it a little bit to make it easier to read.
Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f Reviewed-on: https://gem5-review.googlesource.com/7421 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12272:bcc67ee98e6d |
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12-May-2016 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
sim: Implement load_addr_mask auto-calculation
Recent Linux kernels for AArch64 have changed their start addresses but we still want to relocate the kernel to 0x80080000 which required hacking the load_addr_mask in Realview.py to be 0x7ffffff from 0xfffffff to mask off the proper number of MSBs to load the kernel in the desired location. To avoid having to make this change in the future again, we auto-calculate the load_addr_mask if it is specified as 0x0 in the System sim-object to find the most restrictive address mask instead of having the configuration specify it. If the configuration does specify the address mask, we use it instead of auto-calculating.
Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2323 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12262:a58c0c323e4f |
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12-Apr-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Add an option to load additional kernel objects
There are cases where it is desirable to load a kernel and a set of additional objects. This can, for example, be useful for testing where the bootstrap code can be loaded from one object (the kernel) and the test proper from another.
This changeset adds this functionality by adding a kernel_extras vector parameter to the System class. Object files in this vector are loaded in order after the kernel when running in full system mode.
Change-Id: I06f57c6a65a17b02eb4267bed0aa829f21bcfa3b Reviewed-on: https://gem5-review.googlesource.com/5703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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#
12122:20512f6810d7 |
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28-Jun-2017 |
Jose Marinho <jose.marinho@arm.com> |
cpu, sim: Add param to force CPUs to wait for GDB
By setting the BaseCPU parameter wait_for_dbg_connection, the GDB server blocks during initialisation waiting for the remote debugger to connect before starting the simulated CPU.
Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c [ Update info message to include remote GDB port, rename param. ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3963 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
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12100:5f19ea125548 |
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17-May-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
kvm: move Kvm check from ARM Kvm GIC to System
The check was nearly completely generic anyway, with the exception of the Kvm CPU type.
This will make it easier for other parts of the codebase to do similar checks.
Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da Reviewed-on: https://gem5-review.googlesource.com/3540 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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11839:dd6df2e47c14 |
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14-Feb-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
sim, kvm: make KvmVM a System parameter
A KVM VM is typically a child of the System object already, but for solving future issues with configuration graph resolution, the most logical way to keep track of this object is for it to be an actual parameter of the System object.
Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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11838:0b311345ac72 |
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14-Feb-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
sim,kvm,arm: fix typos
Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11801:cd7f3a1dbf55 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 4/22] remove redundant M5_pid field from process
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11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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11522:348411ec525a |
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06-Jun-2016 |
Stephan Diestelhorst <stephan.diestelhorst@arm.com> |
sim: Call regStats of base-class as well
We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there.
Patch originally provided by Akash Bagdia at ARM Ltd.
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11420:b48c0ba4f524 |
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12-May-2015 |
David Guillen Fandos <david.guillen@arm.com> |
sim: Adding thermal model support
This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch.
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11146:0fd6976303bc |
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30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT cores) caused failures due to the CPU id assignment logic. The comment about thread assignment (worrying about core 0 not having tid 0) seems not to be valid given that our configuration scripts initialize them in order.
This removes that constraint so a heterogenously threaded sytem can work.
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11005:e7f403b6b76f |
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07-Aug-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
base: Declare a type for context IDs
Context IDs used to be declared as ad hoc (usually as int). This changeset introduces a typedef for ContextIDs and a constant for invalid context IDs.
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10913:38dbdeea7f1f |
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07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor and simplify the drain API
The drain() call currently passes around a DrainManager pointer, which is now completely pointless since there is only ever one global DrainManager in the system. It also contains vestiges from the time when SimObjects had to keep track of their child objects that needed draining.
This changeset moves all of the DrainState handling to the Drainable base class and changes the drain() and drainResume() calls to reflect this. Particularly, the drain() call has been updated to take no parameters (the DrainManager argument isn't needed) and return a DrainState instead of an unsigned integer (there is no point returning anything other than 0 or 1 any more). Drainable objects should return either DrainState::Draining (equivalent to returning 1 in the old system) if they need more time to drain or DrainState::Drained (equivalent to returning 0 in the old system) if they are already in a consistent state. Returning DrainState::Running is considered an error.
Drain done signalling is now done through the signalDrainDone() method in the Drainable class instead of using the DrainManager directly. The new call checks if the state of the object is DrainState::Draining before notifying the drain manager. This means that it is safe to call signalDrainDone() without first checking if the simulator has requested draining. The intention here is to reduce the code needed to implement draining in simple objects.
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10910:32f3d1c454ec |
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07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Make the drain state a global typed enum
The drain state enum is currently a part of the Drainable interface. The same state machine will be used by the DrainManager to identify the global state of the simulator. Make the drain state a global typed enum to better cater for this usage scenario.
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10905:a6ca6831e775 |
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07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section.
* Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections).
* The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects.
* Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
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10834:f7a36ade78c2 |
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15-May-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Don't clear the active CPU vector in System::initState
The system class currently clears the vector of active CPUs in initState(). CPUs are added to the list by registerThreadContext() which is called from BaseCPU::init(). This obviously breaks when the System object is initialized after the CPUs. This changeset removes the offending clear() call since the list will be empty after it has been instantiated anyway.
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10700:417ba77dedb4 |
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16-Feb-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: mmap the backing store with MAP_NORESERVE
This patch ensures we can run simulations with very large simulated memories (at least 64 TB based on some quick runs on a Linux workstation). In essence this allows us to efficiently deal with sparse address maps without having to implement a redirection layer in the backing store.
This opens up for run-time errors if we eventually exhausts the hosts memory and swap space, but this should hopefully never happen.
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10553:c1ad57c53a36 |
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23-Nov-2014 |
Alexandru Dutu <alexandru.dutu@amd.com> |
kvm, x86: Adding support for SE mode execution This patch adds methods in KvmCPU model to handle KVM exits caused by syscall instructions and page faults. These types of exits will be encountered if KvmCPU is run in SE mode.
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10494:ffe6ab7141ab |
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20-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
x86: Fixes to avoid LTO warnings
This patch fixes a few minor issues that caused link-time warnings when using LTO, mainly for x86. The most important change is how the syscall array is created. Previously gcc and clang would complain that the declaration and definition types did not match. The organisation is now changed to match how it is done for ARM, moving the code that was previously in syscalls.cc into process.cc, and having a class variable pointing to the static array.
With these changes, there are no longer any warnings using gcc 4.6.3 with LTO.
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10466:73b7549d979e |
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16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA.
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10375:b1bc989611da |
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19-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Restore ostream flags where needed
This patch ensures we adhere to the normal ostream usage rules, and restore the flags after modifying them.
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10367:bf52480abd01 |
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12-Sep-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by the incorrect use of line continuation within strings. (There's also one consistency change to a similar, but correct, use of line continuation)
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10360:919c02740209 |
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09-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Fix a number of unitialised variables and members
Static analysis unearther a bunch of uninitialised variables and members, and this patch addresses the problem. In all cases these omissions seem benign in the end, but at least fixing them means less false positives next time round.
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10318:98771a936b61 |
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03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Cleanup unused ISA traits constants
This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), aligning the use of int vs Addr etc.
The patch also removes the duplication of PageBytes/PageShift and VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical values and the latter has been removed.
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10282:3ea92bc6393b |
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13-Aug-2014 |
Dam Sunwoo <dam.sunwoo@arm.com> |
sim: remove kernel mapping check for baremetal workloads
Baremetal workloads are specified using the "kernel" parameter, but don't always have the correct address mappings. This patch adds a boolean flag to the system and bypasses the kernel addr mapping checks when running in baremetal mode.
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10255:b71e6c577768 |
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19-Jul-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: remove unused MemoryModeStrings array
The System object has a static MemoryModeStrings array that's (1) unused and (2) redundant, since there's an auto-generated version in the Enums namespace. No point in leaving it in.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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9850:87d6b41749e9 |
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04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it.
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9847:29941c87f7b0 |
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04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
alpha: Move system virtProxy to Alpha only
This patch moves the system virtual port proxy to the Alpha system only to make the resurrection of the NOISA slightly less painful. Alpha is the only ISA that is actually using it.
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9814:7ad2b0186a32 |
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18-Jul-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets the cache line size on the system level.
Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used.
A follow-on patch updates the configuration scripts accordingly.
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9524:d6ffa982a68b |
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15-Feb-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Add a system-global option to bypass caches
Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches.
To make memory mode tests cleaner, the following methods are added to the System class:
* isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed.
The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore.
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9342:6fec8f26e56d |
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02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Move the draining interface into a separate base class
This patch moves the draining interface from SimObject to a separate class that can be used by any object needing draining. However, objects not visible to the Python code (i.e., objects not deriving from SimObject) still depend on their parents informing them when to drain. This patch also gets rid of the CountedDrainEvent (which isn't really an event) and replaces it with a DrainManager.
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9294:8fb03b13de02 |
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15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
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9293:df7c3f99ebca |
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15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Mem: Separate the host and guest views of memory backing store
This patch moves all the memory backing store operations from the independent memory controllers to the global physical memory. The main reason for this patch is to allow address striping in a future set of patches, but at this point it already provides some useful functionality in that it is now possible to change the number of memory controllers and their address mapping in combination with checkpointing. Thus, the host and guest view of the memory backing store are now completely separate.
With this patch, the individual memory controllers are far simpler as all responsibility for serializing/unserializing is moved to the physical memory. Currently, the functionality is more or less moved from AbstractMemory to PhysicalMemory without any major changes. However, in a future patch the physical memory will also resolve any ranges that are interleaved and properly assign the backing store to the memory controllers, and keep the host memory as a single contigous chunk per address range.
Functionality for future extensions which involve CPU virtualization also enable the host to get pointers to the backing store.
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#
9292:e57c7d9736a5 |
|
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Checkpoint: Make system serialize call children
This patch changes how the serialization of the system works. The base class had a non-virtual serialize and unserialize, that was hidden by a function with the same name for a number of subclasses (most likely not intentional as the base class should have been virtual). A few of the derived systems had no specialization at all (e.g. Power and x86 that simply called the System::serialize), but MIPS and Alpha adds additional symbol table entries to the checkpoint.
Instead of overriding the virtual function, the additional entries are now printed through a virtual function (un)serializeSymtab. The reason for not calling System::serialize from the two related systems is that a follow up patch will require the system to also serialize the PhysicalMemory, and if this is done in the base class if ends up being between the general parts and the specialized symbol table.
With this patch, the checkpoint is not modified, as the order of the segments is unchanged.
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#
9187:fd9a83e5178a |
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07-Sep-2012 |
Krishnendra Nathella <Krishnendra.Nathella@arm.com> |
sim: add validation to make sure there is memory where we're loading the kernel
|
#
9172:2f2e4582014f |
|
27-Aug-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
System: Remove redundant call to startupCPU
|
#
9147:05137f17887e |
|
08-Aug-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
System: set kernel to null, if unspecified.
|
#
9142:e9b713df4e1d |
|
06-Aug-2012 |
Steve Reinhardt <steve.reinhardt@amd.com> |
str: add an overloaded startswith() utility method for various string types and use it in a few places.
|
#
9053:9cad1c26c3b3 |
|
05-Jun-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
Mem: add per-master stats to physmem
Added per-master stats (similar to cache stats) to physmem.
|
#
9007:7100059f7bfd |
|
14-May-2012 |
Lena Olson <lena@cs.wisc.edu> |
Mem: Fix size check when allocating physical memory
|
#
8986:4cc63185478b |
|
10-May-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: track if the stats have been enabled and prevent requesting master id
Track the point in the initialization where statistics have been registered. After this point registering new masterIds can no longer work as some SimObjects may have sized stats vectors based on the previous value. If someone tries to register a masterId after this point the simulator executes fatal().
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#
8931:7a1dfb191e3f |
|
06-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range.
All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables.
Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation.
|
#
8922:17f037ad8918 |
|
30-Mar-2012 |
William Wang <william.wang@arm.com> |
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
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#
8885:52bbd95b31ed |
|
09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from.
|
#
8852:c744483edfcf |
|
24-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would not be complete without a port proxy by making the proxies members rathen than dynamically allocated. In essence, if NULL would not be a valid value for the proxy, then we avoid using a pointer to make this clear.
The same approach is used for the methods using these proxies, such as loadSections, that now use references rather than pointers to better reflect the fact that NULL would not be an acceptable value (in fact the code would break and that is how this patch started out).
Overall the concept of "using a reference to express unconditional composition where a NULL pointer is never valid" could be done on a much broader scale throughout the code base, but for now it is only done in the locations affected by the proxies.
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#
8832:247fee427324 |
|
12-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
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#
8826:6cc162805986 |
|
10-Feb-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
sim/system: initialize the pagePtr variable
|
#
8813:223945df5510 |
|
03-Feb-2012 |
Gabe Black <gblack@eecs.umich.edu> |
System: Forgot to qrefresh with my last change.
|
#
8812:8bdfb1947cff |
|
03-Feb-2012 |
Gabe Black <gblack@eecs.umich.edu> |
System: Fix the check which detects running out of physical memory.
The code that checks whether pages allocated by allocPhysPages only checks that the first page fits into physical memory, not that all of them do. This change makes the code check the last page which should work properly. This function used to only allocate one page at a time, so the first page and last page used to be the same thing.
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#
8806:669e93d79ed9 |
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29-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
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#
8799:dac1e33e07b0 |
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28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with the main repo.
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#
8798:adaa92be9037 |
|
16-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge yet again with the main repository.
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#
8795:0909f8ed7aa0 |
|
07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository.
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#
8769:f95b2a679eb0 |
|
30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make the system object more consistent between SE and FS.
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#
8765:659670964330 |
|
16-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make some system funcs available in SE and FS.
|
#
8706:b1838faf3bcc |
|
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy.
The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy
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#
8703:f2ac0bca75df |
|
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Add the system port as a central access point
The system port is used as a globally reachable access point to the memory subsystem. The benefit of using an actual port is that the usual infrastructure is used to resolve any access and thus makes the overall system able to handle distributed memories in any configuration, and also makes the accesses agnostic to the address map. This patch only introduces the port and does not actually use it for anything.
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#
8666:97d873b8b13e |
|
09-Jan-2012 |
Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> |
sim: Enable sampling of run-time for code-sections marked using pseudo insts.
This patch adds a mechanism to collect run time samples for specific portions of a benchmark, using work_begin and work_end pseudo instructions.It also enhances the histogram stat to report geometric mean.
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#
8601:af28085882dc |
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23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable.
The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process.
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#
8460:3893d9d2c6c2 |
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10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Make sure fetch doesn't go off into the weeds during speculation.
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#
8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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#
8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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#
7914:eee5bb0fb8ea |
|
07-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
m5: added work completed monitoring support
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#
7897:d9e8b1fd1a9f |
|
07-Feb-2011 |
Joel Hestness <hestness@cs.utexas.edu> |
mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters for McPAT
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#
7770:6286bb50127e |
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19-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
SE: Fix simulating more than 4GB of RAM in SE mode
This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style.
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#
7733:08d6a773d1b6 |
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08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add checkpointing support
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#
7723:ee4ac00d0774 |
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08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
sim: Use forward declarations for ports.
Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything.
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#
7580:6f77f379a594 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
Loader: Make the load address mask be a parameter of the system rather than a constant.
This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.
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#
7445:dfd04ffc1773 |
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03-Jun-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Minor remote GDB cleanup. Expand the help text on the --remote-gdb-port option so people know you can use it to disable remote gdb without reading the source code, and thus don't waste any time trying to add a separate option to do that. Clean up some gdb-related cruft I found while looking for where one would add a gdb disable option, before I found the comment that told me that I didn't need to do that.
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#
6658:f4de76601762 |
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23-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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#
6029:007c36616f47 |
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15-Apr-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Get rid of the Unallocated thread context state. Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way.
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#
5823:9f7efe90084e |
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30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Errors: Use the correct panic/warn/fatal/info message in some places.
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#
5795:72ce7502dc71 |
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17-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Fix issue 326: glibc non-deterministic because it reads /proc
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#
5718:323cfbfec1a4 |
|
05-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
Right now a single thread cpu 1 could get assigned context Id != 1, depending on the order in which it's registered with the system. To make them match, here is a little change.
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5714:76abee886def |
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02-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
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#
5713:993c7952b930 |
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02-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.
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#
5712:199d31b47f7b |
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02-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
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5530:bbfff6d0c42c |
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11-Aug-2008 |
Nathan Binkert <nate@binkert.org> |
params: Get rid of the remnants of the old style parameter configuration stuff.
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#
5512:755fcaf7a4cf |
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23-Jul-2008 |
Michael Adler <Michael.Adler@intel.com> |
RemoteGDB: add an m5 command line option for setting or disabling remote gdb.
|
#
5222:bb733a878f85 |
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13-Nov-2007 |
Korey Sewell <ksewell@umich.edu> |
Add in files from merge-bare-iron, get them compiling in FS and SE mode
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#
5183:b4decf133fe4 |
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25-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
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#
5034:6186ef720dd4 |
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30-Aug-2007 |
Miles Kaufmann <milesck@eecs.umich.edu> |
params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name))
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4997:e7380529bd2d |
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26-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
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4838:286c4b41f425 |
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02-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
debugSymbolTable is a global variable and only needs to be created once, not once per system
|
#
4762:c94e103c83ad |
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24-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way.
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4194:af4f6022394b |
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09-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
implement ipi stufff for SPARC
src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not)
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4095:44792b4db1b9 |
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22-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Make it easier to turn off the remote debugger
|
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3960:1dca397b2bab |
|
20-Dec-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Initial work to make remote gdb available in SE mode. This is completely untested.
|
#
3812:eaa215123a26 |
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30-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it
configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it
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3536:89aa06409e4d |
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06-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.
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3162:e664ad1ab5fe |
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06-Oct-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
system.cc: Make new_page() check for an out of memory condition
src/sim/system.cc: Make new_page() check for an out of memory condition
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#
2902:695d4683916e |
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13-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add system.mem_mode = ['timing', 'atomic'] update scripts acordingly
configs/test/SysPaths.py: new syspaths from nate, this one allows you to set script, binary, and disk paths like system.dir = 'aouaou' in your script configs/test/fs.py: update for system mem_mode Put small checkpoint example Make clock 1THz configs/test/test.py: src/arch/alpha/freebsd/system.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/system.cc: src/arch/alpha/tru64/system.cc: src/arch/sparc/system.cc: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: update for system mem_mode src/dev/io_device.cc: Use time returned from sendAtomic to delay
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2901:f9a45473ab55 |
|
12-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
memory mode information now contained in system object States are now running, draining, or drained. memory state information moved into system object system parameter is not fs only for cpus Implement drain() support in devices Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: Since se mode has a system, allow access to it Verify that the atomic cpu is connected to an atomic system on resume src/cpu/simple/base.cc: Since se mode has a system, allow access to it src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system Since se mode has a system, allow access to it Verify that the timing cpu is connected to an timing system on resume src/dev/ide_disk.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: src/dev/sinic.cc: src/dev/sinic.hh: Implement drain() support in devices src/python/m5/config.py: Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times src/python/m5/objects/BaseCPU.py: move system parameter out of fs to everyone src/sim/sim_object.cc: src/sim/sim_object.hh: States are now running, draining, or drained. memory state information moved into system object src/sim/system.cc: src/sim/system.hh: memory mode information now contained in system object
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2802:babfc298ac86 |
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26-Jun-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern name should be mangled, but it isn't
|
#
2720:695250d6fa42 |
|
12-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge fixes to make full system compile and run.
src/arch/alpha/linux/system.cc: src/cpu/o3/alpha_cpu_impl.hh: src/sim/system.cc: Merge fixes.
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2716:b9114064d77a |
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11-Jun-2006 |
Nathan Binkert <binkertn@umich.edu> |
Merge iceaxe.:/Volumes/work/research/m5/head into iceaxe.:/Volumes/work/research/m5/merge
src/cpu/simple/base.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: hand merge
|
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2689:dbf969c18a65 |
|
07-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Update copyright.
|
#
2680:246e7104f744 |
|
06-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext.
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2640:266b80dd5eca |
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26-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add names to memory Port objects for tracing.
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2632:1bb2f91485ea |
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22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure.
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