12810SN/A/*
213844Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2019 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
4313349Snikos.nikoleris@arm.com *          Nikos Nikoleris
442810SN/A */
452810SN/A
462810SN/A/**
472810SN/A * @file
482810SN/A * Miss Status and Handling Register (MSHR) definitions.
492810SN/A */
502810SN/A
5111486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh"
5211486Snikos.nikoleris@arm.com
536216Snate@binkert.org#include <cassert>
542810SN/A#include <string>
552810SN/A
5612334Sgabeblack@google.com#include "base/logging.hh"
5712727Snikos.nikoleris@arm.com#include "base/trace.hh"
586216Snate@binkert.org#include "base/types.hh"
598232Snate@binkert.org#include "debug/Cache.hh"
6012727Snikos.nikoleris@arm.com#include "mem/cache/base.hh"
6112727Snikos.nikoleris@arm.com#include "mem/request.hh"
626216Snate@binkert.org#include "sim/core.hh"
632810SN/A
6411375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false),
6511284Sandreas.hansson@arm.com               pendingModified(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6713349Snikos.nikoleris@arm.com               wasWholeLineWrite(false), isForward(false)
682810SN/A{
692810SN/A}
702810SN/A
714903SN/AMSHR::TargetList::TargetList()
7212715Snikos.nikoleris@arm.com    : needsWritable(false), hasUpgrade(false), allocOnFill(false),
7312715Snikos.nikoleris@arm.com      hasFromCache(false)
744903SN/A{}
754903SN/A
764903SN/A
7711740Snikos.nikoleris@arm.comvoid
7811741Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source,
7911741Snikos.nikoleris@arm.com                              bool alloc_on_fill)
804903SN/A{
815875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8211284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8311284Sandreas.hansson@arm.com            needsWritable = true;
844903SN/A        }
854903SN/A
867669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
877669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
887669Ssteve.reinhardt@amd.com        // read-only copy
897669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
904903SN/A            hasUpgrade = true;
914903SN/A        }
9211741Snikos.nikoleris@arm.com
9311741Snikos.nikoleris@arm.com        // potentially re-evaluate whether we should allocate on a fill or
9411741Snikos.nikoleris@arm.com        // not
9511741Snikos.nikoleris@arm.com        allocOnFill = allocOnFill || alloc_on_fill;
9612715Snikos.nikoleris@arm.com
9712715Snikos.nikoleris@arm.com        if (source != Target::FromPrefetcher) {
9812715Snikos.nikoleris@arm.com            hasFromCache = hasFromCache || pkt->fromCache();
9913349Snikos.nikoleris@arm.com
10013349Snikos.nikoleris@arm.com            updateWriteFlags(pkt);
10112715Snikos.nikoleris@arm.com        }
1025318SN/A    }
10311740Snikos.nikoleris@arm.com}
1044908SN/A
10511740Snikos.nikoleris@arm.comvoid
10611740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags()
10711740Snikos.nikoleris@arm.com{
10811740Snikos.nikoleris@arm.com    resetFlags();
10911740Snikos.nikoleris@arm.com    for (auto& t: *this) {
11011741Snikos.nikoleris@arm.com        updateFlags(t.pkt, t.source, t.allocOnFill);
11111740Snikos.nikoleris@arm.com    }
11211740Snikos.nikoleris@arm.com}
11311740Snikos.nikoleris@arm.com
11411740Snikos.nikoleris@arm.cominline void
11511740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
11611741Snikos.nikoleris@arm.com                      Counter order, Target::Source source, bool markPending,
11711741Snikos.nikoleris@arm.com                      bool alloc_on_fill)
11811740Snikos.nikoleris@arm.com{
11911741Snikos.nikoleris@arm.com    updateFlags(pkt, source, alloc_on_fill);
1205318SN/A    if (markPending) {
1219543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
1229543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
1239543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1249543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
12511484Snikos.nikoleris@arm.com        if (mshr != nullptr) {
1264908SN/A            assert(!mshr->downstreamPending);
1274908SN/A            mshr->downstreamPending = true;
12811083Sandreas.hansson@arm.com        } else {
12911083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
13011083Sandreas.hansson@arm.com            markPending = false;
1314908SN/A        }
1324903SN/A    }
1334903SN/A
13411741Snikos.nikoleris@arm.com    emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill);
1354903SN/A}
1364903SN/A
1374903SN/A
1387667Ssteve.reinhardt@amd.comstatic void
1397667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1407667Ssteve.reinhardt@amd.com{
14111286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
14211286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
14311286Sandreas.hansson@arm.com
1447667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1457667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1467667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1477667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1487667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1497667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1507669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1517669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1527669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1537667Ssteve.reinhardt@amd.com    }
15411286Sandreas.hansson@arm.com
15511286Sandreas.hansson@arm.com    if (!has_data) {
15611286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
15711286Sandreas.hansson@arm.com        // new command actually would carry data
15811286Sandreas.hansson@arm.com        assert(!pkt->hasData());
15911286Sandreas.hansson@arm.com
16011286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
16111286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
16211286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
16311286Sandreas.hansson@arm.com            // actually allocate space for the data payload
16411286Sandreas.hansson@arm.com            pkt->allocate();
16511286Sandreas.hansson@arm.com        }
16611286Sandreas.hansson@arm.com    }
1677667Ssteve.reinhardt@amd.com}
1687667Ssteve.reinhardt@amd.com
1697667Ssteve.reinhardt@amd.com
1704903SN/Avoid
1714903SN/AMSHR::TargetList::replaceUpgrades()
1724903SN/A{
1734903SN/A    if (!hasUpgrade)
1744903SN/A        return;
1754903SN/A
17610766Sandreas.hansson@arm.com    for (auto& t : *this) {
17710766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1784903SN/A    }
1794903SN/A
1804903SN/A    hasUpgrade = false;
1814903SN/A}
1824903SN/A
1834903SN/A
1842810SN/Avoid
18512791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending(MSHR::TargetList::iterator begin,
18612791Snikos.nikoleris@arm.com                                         MSHR::TargetList::iterator end)
1874908SN/A{
18812791Snikos.nikoleris@arm.com    for (auto t = begin; t != end; t++) {
18912791Snikos.nikoleris@arm.com        if (t->markedPending) {
1909543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1919543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1929543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1939543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1949543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1959543Ssascha.bischoff@arm.com            // passed through.
19612791Snikos.nikoleris@arm.com            MSHR *mshr = t->pkt->findNextSenderState<MSHR>();
19711484Snikos.nikoleris@arm.com            if (mshr != nullptr) {
1985318SN/A                mshr->clearDownstreamPending();
1995318SN/A            }
20012791Snikos.nikoleris@arm.com            t->markedPending = false;
2014908SN/A        }
2024908SN/A    }
2034908SN/A}
2044908SN/A
20512791Snikos.nikoleris@arm.comvoid
20612791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending()
20712791Snikos.nikoleris@arm.com{
20812791Snikos.nikoleris@arm.com    clearDownstreamPending(begin(), end());
20912791Snikos.nikoleris@arm.com}
21012791Snikos.nikoleris@arm.com
2114908SN/A
2124920SN/Abool
21312823Srmk35@cl.cam.ac.ukMSHR::TargetList::trySatisfyFunctional(PacketPtr pkt)
2144920SN/A{
21510766Sandreas.hansson@arm.com    for (auto& t : *this) {
21612823Srmk35@cl.cam.ac.uk        if (pkt->trySatisfyFunctional(t.pkt)) {
2174920SN/A            return true;
2184920SN/A        }
2194920SN/A    }
2204920SN/A
2214920SN/A    return false;
2224920SN/A}
2234920SN/A
2244920SN/A
2254908SN/Avoid
22610766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
22710766Sandreas.hansson@arm.com                        const std::string &prefix) const
2285314SN/A{
22910766Sandreas.hansson@arm.com    for (auto& t : *this) {
2305875Ssteve.reinhardt@amd.com        const char *s;
23110766Sandreas.hansson@arm.com        switch (t.source) {
2328988SAli.Saidi@ARM.com          case Target::FromCPU:
2338988SAli.Saidi@ARM.com            s = "FromCPU";
2348988SAli.Saidi@ARM.com            break;
2358988SAli.Saidi@ARM.com          case Target::FromSnoop:
2368988SAli.Saidi@ARM.com            s = "FromSnoop";
2378988SAli.Saidi@ARM.com            break;
2388988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2398988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2408988SAli.Saidi@ARM.com            break;
2418988SAli.Saidi@ARM.com          default:
2428988SAli.Saidi@ARM.com            s = "";
2438988SAli.Saidi@ARM.com            break;
2445875Ssteve.reinhardt@amd.com        }
2455875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
24610766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
24711744Snikos.nikoleris@arm.com        ccprintf(os, "\n");
2485314SN/A    }
2495314SN/A}
2505314SN/A
2515314SN/A
2525314SN/Avoid
25310764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
25411197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2552810SN/A{
25610764Sandreas.hansson@arm.com    blkAddr = blk_addr;
25710764Sandreas.hansson@arm.com    blkSize = blk_size;
25810028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
25910764Sandreas.hansson@arm.com    readyTime = when_ready;
2604666SN/A    order = _order;
2614626SN/A    assert(target);
2625730SSteve.Reinhardt@amd.com    isForward = false;
26313349Snikos.nikoleris@arm.com    wasWholeLineWrite = false;
2644626SN/A    _isUncacheable = target->req->isUncacheable();
2654626SN/A    inService = false;
2664908SN/A    downstreamPending = false;
26713349Snikos.nikoleris@arm.com
26813349Snikos.nikoleris@arm.com    targets.init(blkAddr, blkSize);
26913349Snikos.nikoleris@arm.com    deferredTargets.init(blkAddr, blkSize);
27013349Snikos.nikoleris@arm.com
2714626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2725875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2735875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2745875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
27511741Snikos.nikoleris@arm.com    targets.add(target, when_ready, _order, source, true, alloc_on_fill);
27613861Sodanrc@yahoo.com.br
27713861Sodanrc@yahoo.com.br    // All targets must refer to the same block
27813861Sodanrc@yahoo.com.br    assert(target->matchBlockAddr(targets.front().pkt, blkSize));
2792810SN/A}
2802810SN/A
2814908SN/A
2825318SN/Avoid
2835318SN/AMSHR::clearDownstreamPending()
2845318SN/A{
2855318SN/A    assert(downstreamPending);
2865318SN/A    downstreamPending = false;
2875318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2885318SN/A    // responses to
2899725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2905318SN/A}
2915318SN/A
29211375Sandreas.hansson@arm.comvoid
29311284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2944908SN/A{
2954908SN/A    assert(!inService);
29610424Sandreas.hansson@arm.com
2974908SN/A    inService = true;
29811284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2997667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
3007667Ssteve.reinhardt@amd.com
3014908SN/A    if (!downstreamPending) {
3024908SN/A        // let upstream caches know that the request has made it to a
3034908SN/A        // level where it's going to get a response
3049725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
3054908SN/A    }
30613349Snikos.nikoleris@arm.com    // if the line is not considered a whole-line write when sent
30713349Snikos.nikoleris@arm.com    // downstream, make sure it is also not considered a whole-line
30813349Snikos.nikoleris@arm.com    // write when receiving the response, and vice versa
30913349Snikos.nikoleris@arm.com    wasWholeLineWrite = isWholeLineWrite();
3104908SN/A}
3114908SN/A
3124908SN/A
3132810SN/Avoid
3142810SN/AMSHR::deallocate()
3152810SN/A{
3169725Sandreas.hansson@arm.com    assert(targets.empty());
3179725Sandreas.hansson@arm.com    targets.resetFlags();
3189725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
3192810SN/A    inService = false;
3202810SN/A}
3212810SN/A
3222810SN/A/*
3232810SN/A * Adds a target to an MSHR
3242810SN/A */
3252810SN/Avoid
32611197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
32711197Sandreas.hansson@arm.com                     bool alloc_on_fill)
3282810SN/A{
32910768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
33010768Sandreas.hansson@arm.com    // outstanding miss
33110768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
33210768Sandreas.hansson@arm.com
3334903SN/A    // if there's a request already in service for this MSHR, we will
3344903SN/A    // have to defer the new target until after the response if any of
3354903SN/A    // the following are true:
3364903SN/A    // - there are other targets already deferred
3374903SN/A    // - there's a pending invalidate to be applied after the response
3384903SN/A    //   comes back (but before this target is processed)
33912350Snikos.nikoleris@arm.com    // - the MSHR's first (and only) non-deferred target is a cache
34012350Snikos.nikoleris@arm.com    //   maintenance packet
34112350Snikos.nikoleris@arm.com    // - the new target is a cache maintenance packet (this is probably
34212350Snikos.nikoleris@arm.com    //   overly conservative but certainly safe)
34311284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
34411284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
34511284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
34611284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
34712350Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = targets.front().pkt;
34812350Snikos.nikoleris@arm.com    if (pkt->req->isCacheMaintenance() ||
34912350Snikos.nikoleris@arm.com        tgt_pkt->req->isCacheMaintenance() ||
35012350Snikos.nikoleris@arm.com        !deferredTargets.empty() ||
35112350Snikos.nikoleris@arm.com        (inService &&
35212350Snikos.nikoleris@arm.com         (hasPostInvalidate() ||
35312350Snikos.nikoleris@arm.com          (pkt->needsWritable() &&
35412350Snikos.nikoleris@arm.com           (!isPendingModified() || hasPostDowngrade() || isForward))))) {
3554903SN/A        // need to put on deferred list
35612350Snikos.nikoleris@arm.com        if (inService && hasPostInvalidate())
3577667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
35811741Snikos.nikoleris@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true,
35911741Snikos.nikoleris@arm.com                            alloc_on_fill);
3604665SN/A    } else {
3615318SN/A        // No request outstanding, or still OK to append to
3625318SN/A        // outstanding request: append to regular target list.  Only
3635318SN/A        // mark pending if current request hasn't been issued yet
3645318SN/A        // (isn't in service).
36511741Snikos.nikoleris@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
36611741Snikos.nikoleris@arm.com                    alloc_on_fill);
3672810SN/A    }
3684665SN/A}
3694665SN/A
3704902SN/Abool
3714902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3724665SN/A{
37311744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
37411279Sandreas.hansson@arm.com
37511284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
37611279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
37711279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
37812350Snikos.nikoleris@arm.com    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
37912350Snikos.nikoleris@arm.com             !pkt->req->isCacheMaintenance(),
38011744Snikos.nikoleris@arm.com             "%s got snoop %s where needsWritable, "
38111863Snikos.nikoleris@arm.com             "does not match isInvalidate", name(), pkt->print());
38211279Sandreas.hansson@arm.com
3834910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3844903SN/A        // Request has not been issued yet, or it's been issued
3854903SN/A        // locally but is buffered unissued at some downstream cache
3864903SN/A        // which is forwarding us this snoop.  Either way, the packet
3874903SN/A        // we're snooping logically precedes this MSHR's request, so
3884903SN/A        // the snoop has no impact on the MSHR, but must be processed
3894903SN/A        // in the standard way by the cache.  The only exception is
3904903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3914903SN/A        // higher-level cache, and the snoop is invalidating, then our
3924903SN/A        // buffered upgrades must be converted to read exclusives,
3934903SN/A        // since the upper-level cache no longer has a valid copy.
3944903SN/A        // That is, even though the upper-level cache got out on its
3954903SN/A        // local bus first, some other invalidating transaction
3964903SN/A        // reached the global bus before the upgrade did.
39712350Snikos.nikoleris@arm.com        if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
3989725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3999725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
4004903SN/A        }
4014903SN/A
4024902SN/A        return false;
4034902SN/A    }
4044665SN/A
4054903SN/A    // From here on down, the request issued by this MSHR logically
4064903SN/A    // precedes the request we're snooping.
40712350Snikos.nikoleris@arm.com    if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
4084903SN/A        // snooped request still precedes the re-request we'll have to
4094903SN/A        // issue for deferred targets, if any...
4109725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
4114903SN/A    }
4124903SN/A
41312350Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = targets.front().pkt;
41412350Snikos.nikoleris@arm.com    if (hasPostInvalidate() || tgt_pkt->req->isCacheInvalidate()) {
41512350Snikos.nikoleris@arm.com        // a prior snoop has already appended an invalidation or a
41612350Snikos.nikoleris@arm.com        // cache invalidation operation is in progress, so logically
41712350Snikos.nikoleris@arm.com        // we don't have the block anymore; no need for further
41812350Snikos.nikoleris@arm.com        // snooping.
4194902SN/A        return true;
4204665SN/A    }
4214665SN/A
42211284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
4237667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
42411284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
42511284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
42611284Sandreas.hansson@arm.com        //    after we receive data.
4277667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
4287667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
4297667Ssteve.reinhardt@amd.com        //    transaction completes.
43010571Sandreas.hansson@arm.com
43111271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
43211271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
43312350Snikos.nikoleris@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse() &&
43412350Snikos.nikoleris@arm.com                      !pkt->isClean();
43511271Sandreas.hansson@arm.com
43611271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
43711271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
43811271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
43911271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
44011271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
44111271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
44211271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
44311271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
44411271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
44511271Sandreas.hansson@arm.com        // snoop.
44611271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
44712749Sgiacomo.travaglini@arm.com            new Packet(std::make_shared<Request>(*pkt->req), pkt->cmd,
44812749Sgiacomo.travaglini@arm.com                       blkSize, pkt->id);
4494670SN/A
45011490Sandreas.hansson@arm.com        if (will_respond) {
45111284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
45211284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
45311284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
45411284Sandreas.hansson@arm.com            // Modified line
45511284Sandreas.hansson@arm.com            pkt->setCacheResponding();
45611284Sandreas.hansson@arm.com
45711284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
45811284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
45911284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
46011284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
46111284Sandreas.hansson@arm.com
46210821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
46311284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
46411284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
46513844Snikos.nikoleris@arm.com        } else if (isPendingModified() && pkt->isClean()) {
46613844Snikos.nikoleris@arm.com            // this cache doesn't respond to the clean request, a
46713844Snikos.nikoleris@arm.com            // destination xbar will respond to this request, but to
46813844Snikos.nikoleris@arm.com            // do so it needs to know if it should wait for the
46913844Snikos.nikoleris@arm.com            // WriteCleanReq
47013844Snikos.nikoleris@arm.com            pkt->setSatisfied();
4714670SN/A        }
47213844Snikos.nikoleris@arm.com
47310826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
47411741Snikos.nikoleris@arm.com                    downstreamPending && targets.needsWritable, false);
4754670SN/A
47612350Snikos.nikoleris@arm.com        if (pkt->needsWritable() || pkt->isInvalidate()) {
4774670SN/A            // This transaction will take away our pending copy
4787667Ssteve.reinhardt@amd.com            postInvalidate = true;
4794670SN/A        }
4807667Ssteve.reinhardt@amd.com    }
4817667Ssteve.reinhardt@amd.com
48211284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4837667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
48411284Sandreas.hansson@arm.com        // our copy if we had a writable one
4857667Ssteve.reinhardt@amd.com        postDowngrade = true;
48611284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
48711284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
48811284Sandreas.hansson@arm.com        // explicitly asked for one
48911284Sandreas.hansson@arm.com        pkt->setHasSharers();
4904667SN/A    }
4914902SN/A
4924902SN/A    return true;
4934665SN/A}
4944665SN/A
49511742Snikos.nikoleris@arm.comMSHR::TargetList
49611742Snikos.nikoleris@arm.comMSHR::extractServiceableTargets(PacketPtr pkt)
49711742Snikos.nikoleris@arm.com{
49811742Snikos.nikoleris@arm.com    TargetList ready_targets;
49913349Snikos.nikoleris@arm.com    ready_targets.init(blkAddr, blkSize);
50011742Snikos.nikoleris@arm.com    // If the downstream MSHR got an invalidation request then we only
50111742Snikos.nikoleris@arm.com    // service the first of the FromCPU targets and any other
50211742Snikos.nikoleris@arm.com    // non-FromCPU target. This way the remaining FromCPU targets
50311742Snikos.nikoleris@arm.com    // issue a new request and get a fresh copy of the block and we
50411742Snikos.nikoleris@arm.com    // avoid memory consistency violations.
50511742Snikos.nikoleris@arm.com    if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
50611742Snikos.nikoleris@arm.com        auto it = targets.begin();
50711866Ssascha.bischoff@arm.com        assert((it->source == Target::FromCPU) ||
50811866Ssascha.bischoff@arm.com               (it->source == Target::FromPrefetcher));
50911742Snikos.nikoleris@arm.com        ready_targets.push_back(*it);
51011742Snikos.nikoleris@arm.com        it = targets.erase(it);
51111742Snikos.nikoleris@arm.com        while (it != targets.end()) {
51211742Snikos.nikoleris@arm.com            if (it->source == Target::FromCPU) {
51311742Snikos.nikoleris@arm.com                it++;
51411742Snikos.nikoleris@arm.com            } else {
51511742Snikos.nikoleris@arm.com                assert(it->source == Target::FromSnoop);
51611742Snikos.nikoleris@arm.com                ready_targets.push_back(*it);
51711742Snikos.nikoleris@arm.com                it = targets.erase(it);
51811742Snikos.nikoleris@arm.com            }
51911742Snikos.nikoleris@arm.com        }
52011742Snikos.nikoleris@arm.com        ready_targets.populateFlags();
52111742Snikos.nikoleris@arm.com    } else {
52211742Snikos.nikoleris@arm.com        std::swap(ready_targets, targets);
52311742Snikos.nikoleris@arm.com    }
52411742Snikos.nikoleris@arm.com    targets.populateFlags();
52511742Snikos.nikoleris@arm.com
52611742Snikos.nikoleris@arm.com    return ready_targets;
52711742Snikos.nikoleris@arm.com}
5284665SN/A
5294665SN/Abool
5304665SN/AMSHR::promoteDeferredTargets()
5314665SN/A{
53212350Snikos.nikoleris@arm.com    if (targets.empty() && deferredTargets.empty()) {
53312350Snikos.nikoleris@arm.com        // nothing to promote
53412350Snikos.nikoleris@arm.com        return false;
5354665SN/A    }
5364665SN/A
53712350Snikos.nikoleris@arm.com    // the deferred targets can be generally promoted unless they
53812350Snikos.nikoleris@arm.com    // contain a cache maintenance request
5394903SN/A
54012350Snikos.nikoleris@arm.com    // find the first target that is a cache maintenance request
54112350Snikos.nikoleris@arm.com    auto it = std::find_if(deferredTargets.begin(), deferredTargets.end(),
54212350Snikos.nikoleris@arm.com                           [](MSHR::Target &t) {
54312350Snikos.nikoleris@arm.com                               return t.pkt->req->isCacheMaintenance();
54412350Snikos.nikoleris@arm.com                           });
54512350Snikos.nikoleris@arm.com    if (it == deferredTargets.begin()) {
54612350Snikos.nikoleris@arm.com        // if the first deferred target is a cache maintenance packet
54712350Snikos.nikoleris@arm.com        // then we can promote provided the targets list is empty and
54812350Snikos.nikoleris@arm.com        // we can service it on its own
54912350Snikos.nikoleris@arm.com        if (targets.empty()) {
55012350Snikos.nikoleris@arm.com            targets.splice(targets.end(), deferredTargets, it);
55112350Snikos.nikoleris@arm.com        }
55212350Snikos.nikoleris@arm.com    } else {
55312350Snikos.nikoleris@arm.com        // if a cache maintenance operation exists, we promote all the
55412350Snikos.nikoleris@arm.com        // deferred targets that precede it, or all deferred targets
55512350Snikos.nikoleris@arm.com        // otherwise
55612350Snikos.nikoleris@arm.com        targets.splice(targets.end(), deferredTargets,
55712350Snikos.nikoleris@arm.com                       deferredTargets.begin(), it);
55812350Snikos.nikoleris@arm.com    }
55912350Snikos.nikoleris@arm.com
56012350Snikos.nikoleris@arm.com    deferredTargets.populateFlags();
56112350Snikos.nikoleris@arm.com    targets.populateFlags();
5629725Sandreas.hansson@arm.com    order = targets.front().order;
5639725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
5644665SN/A
5654665SN/A    return true;
5662810SN/A}
5672810SN/A
56812793Snikos.nikoleris@arm.comvoid
56912793Snikos.nikoleris@arm.comMSHR::promoteIf(const std::function<bool (Target &)>& pred)
57012793Snikos.nikoleris@arm.com{
57112793Snikos.nikoleris@arm.com    // if any of the deferred targets were upper-level cache
57212793Snikos.nikoleris@arm.com    // requests marked downstreamPending, need to clear that
57312793Snikos.nikoleris@arm.com    assert(!downstreamPending);  // not pending here anymore
57412793Snikos.nikoleris@arm.com
57512793Snikos.nikoleris@arm.com    // find the first target does not satisfy the condition
57612793Snikos.nikoleris@arm.com    auto last_it = std::find_if_not(deferredTargets.begin(),
57712793Snikos.nikoleris@arm.com                                    deferredTargets.end(),
57812793Snikos.nikoleris@arm.com                                    pred);
57912793Snikos.nikoleris@arm.com
58012793Snikos.nikoleris@arm.com    // for the prefix of the deferredTargets [begin(), last_it) clear
58112793Snikos.nikoleris@arm.com    // the downstreamPending flag and move them to the target list
58212793Snikos.nikoleris@arm.com    deferredTargets.clearDownstreamPending(deferredTargets.begin(),
58312793Snikos.nikoleris@arm.com                                           last_it);
58412793Snikos.nikoleris@arm.com    targets.splice(targets.end(), deferredTargets,
58512793Snikos.nikoleris@arm.com                   deferredTargets.begin(), last_it);
58612793Snikos.nikoleris@arm.com    // We need to update the flags for the target lists after the
58712793Snikos.nikoleris@arm.com    // modifications
58812793Snikos.nikoleris@arm.com    deferredTargets.populateFlags();
58912793Snikos.nikoleris@arm.com}
59012793Snikos.nikoleris@arm.com
59112793Snikos.nikoleris@arm.comvoid
59212793Snikos.nikoleris@arm.comMSHR::promoteReadable()
59312793Snikos.nikoleris@arm.com{
59412793Snikos.nikoleris@arm.com    if (!deferredTargets.empty() && !hasPostInvalidate()) {
59512793Snikos.nikoleris@arm.com        // We got a non invalidating response, and we have the block
59612793Snikos.nikoleris@arm.com        // but we have deferred targets which are waiting and they do
59712793Snikos.nikoleris@arm.com        // not need writable. This can happen if the original request
59812793Snikos.nikoleris@arm.com        // was for a cache clean operation and we had a copy of the
59912793Snikos.nikoleris@arm.com        // block. Since we serviced the cache clean operation and we
60012793Snikos.nikoleris@arm.com        // have the block, there's no need to defer the targets, so
60112793Snikos.nikoleris@arm.com        // move them up to the regular target list.
60212793Snikos.nikoleris@arm.com
60312793Snikos.nikoleris@arm.com        auto pred = [](Target &t) {
60412793Snikos.nikoleris@arm.com            assert(t.source == Target::FromCPU);
60512793Snikos.nikoleris@arm.com            return !t.pkt->req->isCacheInvalidate() &&
60612793Snikos.nikoleris@arm.com                   !t.pkt->needsWritable();
60712793Snikos.nikoleris@arm.com        };
60812793Snikos.nikoleris@arm.com        promoteIf(pred);
60912793Snikos.nikoleris@arm.com    }
61012793Snikos.nikoleris@arm.com}
6112810SN/A
6122810SN/Avoid
61311284Sandreas.hansson@arm.comMSHR::promoteWritable()
6144668SN/A{
61511284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
61611177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
61711284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
61811284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
6195270SN/A        // of a pending invalidate).  This can happen if the original
62011284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
62111284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
62211284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
62311284Sandreas.hansson@arm.com        // target list.
62411284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
62511284Sandreas.hansson@arm.com        targets.needsWritable = true;
62612792Snikos.nikoleris@arm.com
62712793Snikos.nikoleris@arm.com        auto pred = [](Target &t) {
62812793Snikos.nikoleris@arm.com            assert(t.source == Target::FromCPU);
62912793Snikos.nikoleris@arm.com            return !t.pkt->req->isCacheInvalidate();
63012793Snikos.nikoleris@arm.com        };
63112793Snikos.nikoleris@arm.com
63212793Snikos.nikoleris@arm.com        promoteIf(pred);
6335270SN/A    }
6344668SN/A}
6354668SN/A
6364668SN/A
6375314SN/Abool
63812823Srmk35@cl.cam.ac.ukMSHR::trySatisfyFunctional(PacketPtr pkt)
6395314SN/A{
6405314SN/A    // For printing, we treat the MSHR as a whole as single entity.
6415314SN/A    // For other requests, we iterate over the individual targets
6425314SN/A    // since that's where the actual data lies.
6435314SN/A    if (pkt->isPrint()) {
64412823Srmk35@cl.cam.ac.uk        pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
6455314SN/A        return false;
6465314SN/A    } else {
64712823Srmk35@cl.cam.ac.uk        return (targets.trySatisfyFunctional(pkt) ||
64812823Srmk35@cl.cam.ac.uk                deferredTargets.trySatisfyFunctional(pkt));
6495314SN/A    }
6505314SN/A}
6515314SN/A
65211375Sandreas.hansson@arm.combool
65312724Snikos.nikoleris@arm.comMSHR::sendPacket(BaseCache &cache)
65411375Sandreas.hansson@arm.com{
65511375Sandreas.hansson@arm.com    return cache.sendMSHRQueuePacket(this);
65611375Sandreas.hansson@arm.com}
6575314SN/A
6584668SN/Avoid
6595314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
6602810SN/A{
66112715Snikos.nikoleris@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
66210764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
66310028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
6645730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
66511741Snikos.nikoleris@arm.com             allocOnFill() ? "AllocOnFill" : "",
66611284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
6675314SN/A             _isUncacheable ? "Unc" : "",
6685314SN/A             inService ? "InSvc" : "",
6695314SN/A             downstreamPending ? "DwnPend" : "",
67011610Snikos.nikoleris@arm.com             postInvalidate ? "PostInv" : "",
67112715Snikos.nikoleris@arm.com             postDowngrade ? "PostDowngr" : "",
67212715Snikos.nikoleris@arm.com             hasFromCache() ? "HasFromCache" : "");
6732810SN/A
67411610Snikos.nikoleris@arm.com    if (!targets.empty()) {
67511610Snikos.nikoleris@arm.com        ccprintf(os, "%s  Targets:\n", prefix);
67611610Snikos.nikoleris@arm.com        targets.print(os, verbosity, prefix + "    ");
67711610Snikos.nikoleris@arm.com    }
6789725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
6795314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
6809725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
6812810SN/A    }
6822810SN/A}
6832810SN/A
6849663Suri.wiener@arm.comstd::string
6859663Suri.wiener@arm.comMSHR::print() const
6869663Suri.wiener@arm.com{
68712637Sodanrc@yahoo.com.br    std::ostringstream str;
6889663Suri.wiener@arm.com    print(str);
6899663Suri.wiener@arm.com    return str.str();
6909663Suri.wiener@arm.com}
69113861Sodanrc@yahoo.com.br
69213861Sodanrc@yahoo.com.brbool
69313861Sodanrc@yahoo.com.brMSHR::matchBlockAddr(const Addr addr, const bool is_secure) const
69413861Sodanrc@yahoo.com.br{
69513861Sodanrc@yahoo.com.br    assert(hasTargets());
69613861Sodanrc@yahoo.com.br    return (blkAddr == addr) && (isSecure == is_secure);
69713861Sodanrc@yahoo.com.br}
69813861Sodanrc@yahoo.com.br
69913861Sodanrc@yahoo.com.brbool
70013861Sodanrc@yahoo.com.brMSHR::matchBlockAddr(const PacketPtr pkt) const
70113861Sodanrc@yahoo.com.br{
70213861Sodanrc@yahoo.com.br    assert(hasTargets());
70313861Sodanrc@yahoo.com.br    return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
70413861Sodanrc@yahoo.com.br}
70513861Sodanrc@yahoo.com.br
70613861Sodanrc@yahoo.com.brbool
70713861Sodanrc@yahoo.com.brMSHR::conflictAddr(const QueueEntry* entry) const
70813861Sodanrc@yahoo.com.br{
70913861Sodanrc@yahoo.com.br    assert(hasTargets());
71013861Sodanrc@yahoo.com.br    return entry->matchBlockAddr(blkAddr, isSecure);
71113861Sodanrc@yahoo.com.br}
712