1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Steve Reinhardt
42 *          Andreas Hansson
43 */
44
45/**
46 * @file
47 * Declaration of a memory-mapped bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#ifndef __MEM_BRIDGE_HH__
52#define __MEM_BRIDGE_HH__
53
54#include <deque>
55
56#include "base/types.hh"
57#include "mem/port.hh"
58#include "params/Bridge.hh"
59#include "sim/clocked_object.hh"
60
61/**
62 * A bridge is used to interface two different crossbars (or in general a
63 * memory-mapped master and slave), with buffering for requests and
64 * responses. The bridge has a fixed delay for packets passing through
65 * it and responds to a fixed set of address ranges.
66 *
67 * The bridge comprises a slave port and a master port, that buffer
68 * outgoing responses and requests respectively. Buffer space is
69 * reserved when a request arrives, also reserving response space
70 * before forwarding the request. If there is no space present, then
71 * the bridge will delay accepting the packet until space becomes
72 * available.
73 */
74class Bridge : public ClockedObject
75{
76  protected:
77
78    /**
79     * A deferred packet stores a packet along with its scheduled
80     * transmission time
81     */
82    class DeferredPacket
83    {
84
85      public:
86
87        const Tick tick;
88        const PacketPtr pkt;
89
90        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
91        { }
92    };
93
94    // Forward declaration to allow the slave port to have a pointer
95    class BridgeMasterPort;
96
97    /**
98     * The port on the side that receives requests and sends
99     * responses. The slave port has a set of address ranges that it
100     * is responsible for. The slave port also has a buffer for the
101     * responses not yet sent.
102     */
103    class BridgeSlavePort : public SlavePort
104    {
105
106      private:
107
108        /** The bridge to which this port belongs. */
109        Bridge& bridge;
110
111        /**
112         * Master port on the other side of the bridge.
113         */
114        BridgeMasterPort& masterPort;
115
116        /** Minimum request delay though this bridge. */
117        const Cycles delay;
118
119        /** Address ranges to pass through the bridge */
120        const AddrRangeList ranges;
121
122        /**
123         * Response packet queue. Response packets are held in this
124         * queue for a specified delay to model the processing delay
125         * of the bridge. We use a deque as we need to iterate over
126         * the items for functional accesses.
127         */
128        std::deque<DeferredPacket> transmitList;
129
130        /** Counter to track the outstanding responses. */
131        unsigned int outstandingResponses;
132
133        /** If we should send a retry when space becomes available. */
134        bool retryReq;
135
136        /** Max queue size for reserved responses. */
137        unsigned int respQueueLimit;
138
139        /**
140         * Upstream caches need this packet until true is returned, so
141         * hold it for deletion until a subsequent call
142         */
143        std::unique_ptr<Packet> pendingDelete;
144
145        /**
146         * Is this side blocked from accepting new response packets.
147         *
148         * @return true if the reserved space has reached the set limit
149         */
150        bool respQueueFull() const;
151
152        /**
153         * Handle send event, scheduled when the packet at the head of
154         * the response queue is ready to transmit (for timing
155         * accesses only).
156         */
157        void trySendTiming();
158
159        /** Send event for the response queue. */
160        EventFunctionWrapper sendEvent;
161
162      public:
163
164        /**
165         * Constructor for the BridgeSlavePort.
166         *
167         * @param _name the port name including the owner
168         * @param _bridge the structural owner
169         * @param _masterPort the master port on the other side of the bridge
170         * @param _delay the delay in cycles from receiving to sending
171         * @param _resp_limit the size of the response queue
172         * @param _ranges a number of address ranges to forward
173         */
174        BridgeSlavePort(const std::string& _name, Bridge& _bridge,
175                        BridgeMasterPort& _masterPort, Cycles _delay,
176                        int _resp_limit, std::vector<AddrRange> _ranges);
177
178        /**
179         * Queue a response packet to be sent out later and also schedule
180         * a send if necessary.
181         *
182         * @param pkt a response to send out after a delay
183         * @param when tick when response packet should be sent
184         */
185        void schedTimingResp(PacketPtr pkt, Tick when);
186
187        /**
188         * Retry any stalled request that we have failed to accept at
189         * an earlier point in time. This call will do nothing if no
190         * request is waiting.
191         */
192        void retryStalledReq();
193
194      protected:
195
196        /** When receiving a timing request from the peer port,
197            pass it to the bridge. */
198        bool recvTimingReq(PacketPtr pkt);
199
200        /** When receiving a retry request from the peer port,
201            pass it to the bridge. */
202        void recvRespRetry();
203
204        /** When receiving a Atomic requestfrom the peer port,
205            pass it to the bridge. */
206        Tick recvAtomic(PacketPtr pkt);
207
208        /** When receiving a Functional request from the peer port,
209            pass it to the bridge. */
210        void recvFunctional(PacketPtr pkt);
211
212        /** When receiving a address range request the peer port,
213            pass it to the bridge. */
214        AddrRangeList getAddrRanges() const;
215    };
216
217
218    /**
219     * Port on the side that forwards requests and receives
220     * responses. The master port has a buffer for the requests not
221     * yet sent.
222     */
223    class BridgeMasterPort : public MasterPort
224    {
225
226      private:
227
228        /** The bridge to which this port belongs. */
229        Bridge& bridge;
230
231        /**
232         * The slave port on the other side of the bridge.
233         */
234        BridgeSlavePort& slavePort;
235
236        /** Minimum delay though this bridge. */
237        const Cycles delay;
238
239        /**
240         * Request packet queue. Request packets are held in this
241         * queue for a specified delay to model the processing delay
242         * of the bridge.  We use a deque as we need to iterate over
243         * the items for functional accesses.
244         */
245        std::deque<DeferredPacket> transmitList;
246
247        /** Max queue size for request packets */
248        const unsigned int reqQueueLimit;
249
250        /**
251         * Handle send event, scheduled when the packet at the head of
252         * the outbound queue is ready to transmit (for timing
253         * accesses only).
254         */
255        void trySendTiming();
256
257        /** Send event for the request queue. */
258        EventFunctionWrapper sendEvent;
259
260      public:
261
262        /**
263         * Constructor for the BridgeMasterPort.
264         *
265         * @param _name the port name including the owner
266         * @param _bridge the structural owner
267         * @param _slavePort the slave port on the other side of the bridge
268         * @param _delay the delay in cycles from receiving to sending
269         * @param _req_limit the size of the request queue
270         */
271        BridgeMasterPort(const std::string& _name, Bridge& _bridge,
272                         BridgeSlavePort& _slavePort, Cycles _delay,
273                         int _req_limit);
274
275        /**
276         * Is this side blocked from accepting new request packets.
277         *
278         * @return true if the occupied space has reached the set limit
279         */
280        bool reqQueueFull() const;
281
282        /**
283         * Queue a request packet to be sent out later and also schedule
284         * a send if necessary.
285         *
286         * @param pkt a request to send out after a delay
287         * @param when tick when response packet should be sent
288         */
289        void schedTimingReq(PacketPtr pkt, Tick when);
290
291        /**
292         * Check a functional request against the packets in our
293         * request queue.
294         *
295         * @param pkt packet to check against
296         *
297         * @return true if we find a match
298         */
299        bool trySatisfyFunctional(PacketPtr pkt);
300
301      protected:
302
303        /** When receiving a timing request from the peer port,
304            pass it to the bridge. */
305        bool recvTimingResp(PacketPtr pkt);
306
307        /** When receiving a retry request from the peer port,
308            pass it to the bridge. */
309        void recvReqRetry();
310    };
311
312    /** Slave port of the bridge. */
313    BridgeSlavePort slavePort;
314
315    /** Master port of the bridge. */
316    BridgeMasterPort masterPort;
317
318  public:
319
320    Port &getPort(const std::string &if_name,
321                  PortID idx=InvalidPortID) override;
322
323    void init() override;
324
325    typedef BridgeParams Params;
326
327    Bridge(Params *p);
328};
329
330#endif //__MEM_BRIDGE_HH__
331