1# -*- mode:python -*-
2#
3# Copyright (c) 2018 ARM Limited
4# All rights reserved
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder.  You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Copyright (c) 2006 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Nathan Binkert
42
43Import('*')
44
45SimObject('CommMonitor.py')
46Source('comm_monitor.cc')
47
48SimObject('AbstractMemory.py')
49SimObject('AddrMapper.py')
50SimObject('Bridge.py')
51SimObject('DRAMCtrl.py')
52SimObject('ExternalMaster.py')
53SimObject('ExternalSlave.py')
54SimObject('MemObject.py')
55SimObject('SimpleMemory.py')
56SimObject('XBar.py')
57SimObject('HMCController.py')
58SimObject('SerialLink.py')
59SimObject('MemDelay.py')
60
61Source('abstract_mem.cc')
62Source('addr_mapper.cc')
63Source('bridge.cc')
64Source('coherent_xbar.cc')
65Source('drampower.cc')
66Source('dram_ctrl.cc')
67Source('external_master.cc')
68Source('external_slave.cc')
69Source('noncoherent_xbar.cc')
70Source('packet.cc')
71Source('port.cc')
72Source('packet_queue.cc')
73Source('port_proxy.cc')
74Source('physical.cc')
75Source('secure_port_proxy.cc')
76Source('simple_mem.cc')
77Source('snoop_filter.cc')
78Source('stack_dist_calc.cc')
79Source('tport.cc')
80Source('xbar.cc')
81Source('hmc_controller.cc')
82Source('serial_link.cc')
83Source('mem_delay.cc')
84
85if env['TARGET_ISA'] != 'null':
86    Source('fs_translating_port_proxy.cc')
87    Source('se_translating_port_proxy.cc')
88    Source('page_table.cc')
89
90if env['HAVE_DRAMSIM']:
91    SimObject('DRAMSim2.py')
92    Source('dramsim2_wrapper.cc')
93    Source('dramsim2.cc')
94
95SimObject('MemChecker.py')
96Source('mem_checker.cc')
97Source('mem_checker_monitor.cc')
98
99DebugFlag('AddrRanges')
100DebugFlag('BaseXBar')
101DebugFlag('CoherentXBar')
102DebugFlag('NoncoherentXBar')
103DebugFlag('SnoopFilter')
104CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
105                      'SnoopFilter'])
106
107DebugFlag('Bridge')
108DebugFlag('CommMonitor')
109DebugFlag('DRAM')
110DebugFlag('DRAMPower')
111DebugFlag('DRAMState')
112DebugFlag('ExternalPort')
113DebugFlag('LLSC')
114DebugFlag('MMU')
115DebugFlag('MemoryAccess')
116DebugFlag('PacketQueue')
117DebugFlag('StackDist')
118DebugFlag("DRAMSim2")
119DebugFlag('HMCController')
120DebugFlag('SerialLink')
121
122DebugFlag("MemChecker")
123DebugFlag("MemCheckerMonitor")
124DebugFlag("QOS")
125