1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Lisa Hsu
40
41from __future__ import print_function
42from __future__ import absolute_import
43
44from m5.defines import buildEnv
45from m5.objects import *
46
47# Base implementations of L1, L2, IO and TLB-walker caches. There are
48# used in the regressions and also as base components in the
49# system-configuration scripts. The values are meant to serve as a
50# starting point, and specific parameters can be overridden in the
51# specific instantiations.
52
53class L1Cache(Cache):
54    assoc = 2
55    tag_latency = 2
56    data_latency = 2
57    response_latency = 2
58    mshrs = 4
59    tgts_per_mshr = 20
60
61class L1_ICache(L1Cache):
62    is_read_only = True
63    # Writeback clean lines as well
64    writeback_clean = True
65
66class L1_DCache(L1Cache):
67    pass
68
69class L2Cache(Cache):
70    assoc = 8
71    tag_latency = 20
72    data_latency = 20
73    response_latency = 20
74    mshrs = 20
75    tgts_per_mshr = 12
76    write_buffers = 8
77
78class IOCache(Cache):
79    assoc = 8
80    tag_latency = 50
81    data_latency = 50
82    response_latency = 50
83    mshrs = 20
84    size = '1kB'
85    tgts_per_mshr = 12
86
87class PageTableWalkerCache(Cache):
88    assoc = 2
89    tag_latency = 2
90    data_latency = 2
91    response_latency = 2
92    mshrs = 10
93    size = '1kB'
94    tgts_per_mshr = 12
95
96    # the x86 table walker actually writes to the table-walker cache
97    if buildEnv['TARGET_ISA'] == 'x86':
98        is_read_only = False
99    else:
100        is_read_only = True
101        # Writeback clean lines as well
102        writeback_clean = True
103