Searched refs:ns (Results 1 - 25 of 35) sorted by relevance

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/gem5/src/sim/
H A Dcore.cc55 double ns; member in namespace:SimClock::Float
68 Tick ns; member in namespace:SimClock::Int
94 Float::ns = Float::s / 1.0e9; member in class:Float
100 Float::GHz = 1.0 / Float::ns;
105 Int::ns = Int::us / 1000; member in class:Int
106 Int::ps = Int::ns / 1000;
H A Dcore.hh65 extern double ns; ///< nanosecond
88 extern Tick ns; ///< nanosecond
H A Dpseudo_inst.cc256 quiesceNs(ThreadContext *tc, uint64_t ns) argument
258 DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns);
259 tc->quiesceTick(curTick() + SimClock::Int::ns * ns); local
275 SimClock::Int::ns;
282 return curTick() / SimClock::Int::ns;
307 Tick when = curTick() + delay * SimClock::Int::ns;
316 Tick when = curTick() + delay * SimClock::Int::ns;
442 Tick when = curTick() + delay * SimClock::Int::ns;
443 Tick repeat = period * SimClock::Int::ns;
[all...]
H A Dpseudo_inst.hh69 void quiesceNs(ThreadContext *tc, uint64_t ns);
/gem5/src/cpu/kvm/
H A Dtimer.hh130 Tick ticksFromHostNs(uint64_t ns) { argument
131 return ns * hostFactor * SimClock::Float::ns;
149 return ticks / (SimClock::Float::ns * hostFactor);
/gem5/util/m5/jni/
H A Dgem5Op.java49 public native void quiesceNs(long ns); argument
/gem5/src/arch/arm/
H A Dpagetable.hh132 bool ns; member in struct:ArmISA::TlbEntry
157 ns(true), nstid(true), el(EL0), nonCacheable(uncacheable),
172 ns(true), nstid(true), el(EL0), nonCacheable(false),
272 newBits |= ns << 9; // NS bit
290 "ns:%d nstid:%d g:%d el:%d", vpn << N, asid, vmid,
291 isHyp, pfn << N, size, ap, ns, nstid, global, el);
307 SERIALIZE_SCALAR(ns); variable
337 UNSERIALIZE_SCALAR(ns); variable
H A Disa.cc499 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
842 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
1060 if (haveSecurity && !highestELIs64 && !scr.ns) {
1114 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1124 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1134 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1144 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1159 haveSecurity && !scr.ns,
1174 haveSecurity && !scr.ns,
1188 haveSecurity && !scr.ns,
[all...]
H A Dfaults.cc519 if (scr.ns) {
520 scr.ns = 0;
803 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
875 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1181 return (!scr.ns || scr.aw);
1290 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1351 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1461 return (!scr.ns || scr.aw);
1500 return (!scr.ns || scr.aw);
1512 return (!scr.ns || sc
[all...]
H A Dutility.cc208 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
792 ok &= (mode != MODE_MON) || !scr.ns;
804 ok &= (mode != MODE_MON) || !scr.ns;
H A Dtlb.cc181 "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d "
186 retval ? retval->ns : 0, retval ? retval->nstid : 0,
199 " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn,
202 entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid,
207 "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n",
210 table[size-1].size, table[size-1].ap, table[size-1].ns,
758 (isSecure && te->ns && scr.sif))) {
761 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n",
762 ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe);
991 "AP:%d priv:%d write:%d ns
[all...]
H A Dutility.hh249 return !scr.ns;
H A Dmiscregs_types.hh311 Bitfield<0> ns; member in namespace:ArmISA
628 Bitfield<9> ns; member in namespace:ArmISA
H A Disa.hh659 snsBankedIndex64(MiscRegIndex reg, bool ns) const
663 reg_as_int += (haveSecurity && !ns) ? 2 : 1;
/gem5/util/m5/
H A Dlua_gem5Op.c59 uint64_t ns = lua_tointeger(L, 1); local
60 m5_quiesce_ns(ns);
75 uint64_t ns = m5_quiesce_time(); local
76 lua_pushinteger(L, ns);
83 uint64_t ns = m5_rpns(); local
84 lua_pushinteger(L, ns);
/gem5/src/systemc/core/
H A Dprocess.hh69 void needsStart(bool ns) { _needsStart = ns; } argument
/gem5/include/gem5/
H A Dm5ops.h45 void m5_quiesce_ns(uint64_t ns);
/gem5/src/mem/
H A Ddramsim2.cc60 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
151 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
159 // 50 ns is just an arbitrary value at this point
290 wrapper.clockPeriod() * SimClock::Int::ns));
318 wrapper.clockPeriod() * SimClock::Int::ns));
H A Ddrampower.cc97 // Clock period in ns
98 timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
/gem5/src/base/
H A Dtime.cc70 static_cast<uint64_t>(nsec() * SimClock::Float::ns);
/gem5/src/dev/serial/
H A Duart8250.cc79 static const Tick interval = 225 * SimClock::Int::ns;
208 if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
/gem5/src/dev/arm/
H A Denergy_ctrl.cc104 result = dvfsHandler->transLatency() / SimClock::Int::ns;
105 DPRINTF(EnergyCtrl, "reading dvfs handler trans latency %d ns\n",
H A Dgic_v3_redistributor.hh220 void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
H A Dgic_v3_redistributor.cc716 Gicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns) argument
723 if (ns) {
/gem5/ext/pybind11/include/pybind11/detail/
H A Dcommon.h524 template <typename... Ts> constexpr size_t constexpr_sum(Ts... ns) { return (0 + ... + size_t{ns}); } argument
528 constexpr size_t constexpr_sum(T n, Ts... ns) { return size_t{n} + constexpr_sum(ns...); } argument

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