113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/utility.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913690Sjairo.balart@metempsy.com#include "mem/fs_translating_port_proxy.hh" 5013531Sjairo.balart@metempsy.com 5113531Sjairo.balart@metempsy.comconst AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400, 5213756Sjairo.balart@metempsy.com SGI_base + 0x041f); 5313531Sjairo.balart@metempsy.com 5413531Sjairo.balart@metempsy.comGicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : gic(gic), 5613531Sjairo.balart@metempsy.com distributor(nullptr), 5713531Sjairo.balart@metempsy.com cpuInterface(nullptr), 5813531Sjairo.balart@metempsy.com cpuId(cpu_id), 5913928Sgiacomo.travaglini@arm.com memProxy(nullptr), 6014258Sgiacomo.travaglini@arm.com peInLowPowerState(true), 6114258Sgiacomo.travaglini@arm.com irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0), 6214258Sgiacomo.travaglini@arm.com irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false), 6314258Sgiacomo.travaglini@arm.com irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false), 6414258Sgiacomo.travaglini@arm.com irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false), 6514258Sgiacomo.travaglini@arm.com irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0), 6614258Sgiacomo.travaglini@arm.com irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX, Gicv3::INT_EDGE_TRIGGERED), 6714258Sgiacomo.travaglini@arm.com irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0), 6814258Sgiacomo.travaglini@arm.com irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0), 6914258Sgiacomo.travaglini@arm.com DPG1S(false), 7014258Sgiacomo.travaglini@arm.com DPG1NS(false), 7114258Sgiacomo.travaglini@arm.com DPG0(false), 7214258Sgiacomo.travaglini@arm.com EnableLPIs(false), 7314258Sgiacomo.travaglini@arm.com lpiConfigurationTablePtr(0), 7414258Sgiacomo.travaglini@arm.com lpiIDBits(0), 7514258Sgiacomo.travaglini@arm.com lpiPendingTablePtr(0), 7613878Sgiacomo.travaglini@arm.com addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000) 7713531Sjairo.balart@metempsy.com{ 7813531Sjairo.balart@metempsy.com} 7913531Sjairo.balart@metempsy.com 8013531Sjairo.balart@metempsy.comvoid 8113531Sjairo.balart@metempsy.comGicv3Redistributor::init() 8213531Sjairo.balart@metempsy.com{ 8313531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 8413531Sjairo.balart@metempsy.com cpuInterface = gic->getCPUInterface(cpuId); 8513928Sgiacomo.travaglini@arm.com 8613928Sgiacomo.travaglini@arm.com memProxy = &gic->getSystem()->physProxy; 8713531Sjairo.balart@metempsy.com} 8813531Sjairo.balart@metempsy.com 8913531Sjairo.balart@metempsy.comuint64_t 9013531Sjairo.balart@metempsy.comGicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access) 9113531Sjairo.balart@metempsy.com{ 9213531Sjairo.balart@metempsy.com if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers 9313531Sjairo.balart@metempsy.com uint64_t value = 0; 9413531Sjairo.balart@metempsy.com int first_intid = addr - GICR_IPRIORITYR.start(); 9513531Sjairo.balart@metempsy.com 9613531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < size; i++, int_id++) { 9713531Sjairo.balart@metempsy.com uint8_t prio = irqPriority[int_id]; 9813531Sjairo.balart@metempsy.com 9913531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 10013531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 10113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 10213531Sjairo.balart@metempsy.com continue; 10313531Sjairo.balart@metempsy.com } else { 10413531Sjairo.balart@metempsy.com // NS view 10513531Sjairo.balart@metempsy.com prio = (prio << 1) & 0xff; 10613531Sjairo.balart@metempsy.com } 10713531Sjairo.balart@metempsy.com } 10813531Sjairo.balart@metempsy.com 10913531Sjairo.balart@metempsy.com value |= prio << (i * 8); 11013531Sjairo.balart@metempsy.com } 11113531Sjairo.balart@metempsy.com 11213531Sjairo.balart@metempsy.com return value; 11313531Sjairo.balart@metempsy.com } 11413531Sjairo.balart@metempsy.com 11513531Sjairo.balart@metempsy.com switch (addr) { 11613531Sjairo.balart@metempsy.com case GICR_CTLR: { // Control Register 11713531Sjairo.balart@metempsy.com uint64_t value = 0; 11813531Sjairo.balart@metempsy.com 11913531Sjairo.balart@metempsy.com if (DPG1S) { 12013531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG1S; 12113531Sjairo.balart@metempsy.com } 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com if (DPG1NS) { 12413531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG1NS; 12513531Sjairo.balart@metempsy.com } 12613531Sjairo.balart@metempsy.com 12713531Sjairo.balart@metempsy.com if (DPG0) { 12813531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG0; 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13113690Sjairo.balart@metempsy.com if (EnableLPIs) { 13213690Sjairo.balart@metempsy.com value |= GICR_CTLR_ENABLE_LPIS; 13313690Sjairo.balart@metempsy.com } 13413690Sjairo.balart@metempsy.com 13513531Sjairo.balart@metempsy.com return value; 13613531Sjairo.balart@metempsy.com } 13713531Sjairo.balart@metempsy.com 13813531Sjairo.balart@metempsy.com case GICR_IIDR: // Implementer Identification Register 13913531Sjairo.balart@metempsy.com //return 0x43b; // r0p0 GIC-500 14013531Sjairo.balart@metempsy.com return 0; 14113531Sjairo.balart@metempsy.com 14213531Sjairo.balart@metempsy.com case GICR_TYPER: { // Type Register 14313531Sjairo.balart@metempsy.com /* 14413531Sjairo.balart@metempsy.com * Affinity_Value [63:32] == X 14513531Sjairo.balart@metempsy.com * (The identity of the PE associated with this Redistributor) 14613531Sjairo.balart@metempsy.com * CommonLPIAff [25:24] == 01 14713531Sjairo.balart@metempsy.com * (All Redistributors with the same Aff3 value must share an 14813531Sjairo.balart@metempsy.com * LPI Configuration table) 14913531Sjairo.balart@metempsy.com * Processor_Number [23:8] == X 15013531Sjairo.balart@metempsy.com * (A unique identifier for the PE) 15113531Sjairo.balart@metempsy.com * DPGS [5] == 1 15213531Sjairo.balart@metempsy.com * (GICR_CTLR.DPG* bits are supported) 15313531Sjairo.balart@metempsy.com * Last [4] == X 15413531Sjairo.balart@metempsy.com * (This Redistributor is the highest-numbered Redistributor in 15513531Sjairo.balart@metempsy.com * a series of contiguous Redistributor pages) 15613690Sjairo.balart@metempsy.com * DirectLPI [3] == 1 15713690Sjairo.balart@metempsy.com * (direct injection of LPIs supported) 15813531Sjairo.balart@metempsy.com * VLPIS [1] == 0 15913531Sjairo.balart@metempsy.com * (virtual LPIs not supported) 16013690Sjairo.balart@metempsy.com * PLPIS [0] == 1 16113690Sjairo.balart@metempsy.com * (physical LPIs supported) 16213531Sjairo.balart@metempsy.com */ 16313531Sjairo.balart@metempsy.com uint64_t affinity = getAffinity(); 16413531Sjairo.balart@metempsy.com int last = cpuId == (gic->getSystem()->numContexts() - 1); 16513531Sjairo.balart@metempsy.com return (affinity << 32) | (1 << 24) | (cpuId << 8) | 16613690Sjairo.balart@metempsy.com (1 << 5) | (last << 4) | (1 << 3) | (1 << 0); 16713531Sjairo.balart@metempsy.com } 16813531Sjairo.balart@metempsy.com 16913531Sjairo.balart@metempsy.com case GICR_WAKER: // Wake Register 17013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 17113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 17213531Sjairo.balart@metempsy.com return 0; 17313531Sjairo.balart@metempsy.com } 17413531Sjairo.balart@metempsy.com 17513531Sjairo.balart@metempsy.com if (peInLowPowerState) { 17613531Sjairo.balart@metempsy.com return GICR_WAKER_ChildrenAsleep | GICR_WAKER_ProcessorSleep; 17713531Sjairo.balart@metempsy.com } else { 17813531Sjairo.balart@metempsy.com return 0; 17913531Sjairo.balart@metempsy.com } 18013531Sjairo.balart@metempsy.com 18113531Sjairo.balart@metempsy.com case GICR_PIDR0: { // Peripheral ID0 Register 18213756Sjairo.balart@metempsy.com return 0x92; // Part number, bits[7:0] 18313531Sjairo.balart@metempsy.com } 18413531Sjairo.balart@metempsy.com 18513531Sjairo.balart@metempsy.com case GICR_PIDR1: { // Peripheral ID1 Register 18613531Sjairo.balart@metempsy.com uint8_t des_0 = 0xB; // JEP106 identification code, bits[3:0] 18713531Sjairo.balart@metempsy.com uint8_t part_1 = 0x4; // Part number, bits[11:8] 18813531Sjairo.balart@metempsy.com return (des_0 << 4) | (part_1 << 0); 18913531Sjairo.balart@metempsy.com } 19013531Sjairo.balart@metempsy.com 19113531Sjairo.balart@metempsy.com case GICR_PIDR2: { // Peripheral ID2 Register 19213531Sjairo.balart@metempsy.com uint8_t arch_rev = 0x3; // 0x3 GICv3 19313531Sjairo.balart@metempsy.com uint8_t jedec = 0x1; // JEP code 19413531Sjairo.balart@metempsy.com uint8_t des_1 = 0x3; // JEP106 identification code, bits[6:4] 19513531Sjairo.balart@metempsy.com return (arch_rev << 4) | (jedec << 3) | (des_1 << 0); 19613531Sjairo.balart@metempsy.com } 19713531Sjairo.balart@metempsy.com 19813531Sjairo.balart@metempsy.com case GICR_PIDR3: // Peripheral ID3 Register 19913531Sjairo.balart@metempsy.com return 0x0; // Implementation defined 20013531Sjairo.balart@metempsy.com 20113531Sjairo.balart@metempsy.com case GICR_PIDR4: { // Peripheral ID4 Register 20213531Sjairo.balart@metempsy.com uint8_t size = 0x4; // 64 KB software visible page 20313531Sjairo.balart@metempsy.com uint8_t des_2 = 0x4; // ARM implementation 20413531Sjairo.balart@metempsy.com return (size << 4) | (des_2 << 0); 20513531Sjairo.balart@metempsy.com } 20613531Sjairo.balart@metempsy.com 20713531Sjairo.balart@metempsy.com case GICR_PIDR5: // Peripheral ID5 Register 20813531Sjairo.balart@metempsy.com case GICR_PIDR6: // Peripheral ID6 Register 20913531Sjairo.balart@metempsy.com case GICR_PIDR7: // Peripheral ID7 Register 21013531Sjairo.balart@metempsy.com return 0; // RES0 21113531Sjairo.balart@metempsy.com 21213531Sjairo.balart@metempsy.com case GICR_IGROUPR0: { // Interrupt Group Register 0 21313531Sjairo.balart@metempsy.com uint64_t value = 0; 21413531Sjairo.balart@metempsy.com 21513531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 21613531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 21713531Sjairo.balart@metempsy.com return 0; 21813531Sjairo.balart@metempsy.com } 21913531Sjairo.balart@metempsy.com 22013531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 22113531Sjairo.balart@metempsy.com value |= (irqGroup[int_id] << int_id); 22213531Sjairo.balart@metempsy.com } 22313531Sjairo.balart@metempsy.com 22413531Sjairo.balart@metempsy.com return value; 22513531Sjairo.balart@metempsy.com } 22613531Sjairo.balart@metempsy.com 22713531Sjairo.balart@metempsy.com case GICR_ISENABLER0: // Interrupt Set-Enable Register 0 22813531Sjairo.balart@metempsy.com case GICR_ICENABLER0: { // Interrupt Clear-Enable Register 0 22913531Sjairo.balart@metempsy.com uint64_t value = 0; 23013531Sjairo.balart@metempsy.com 23113531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 23213531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 23313531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 23413531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 23513531Sjairo.balart@metempsy.com continue; 23613531Sjairo.balart@metempsy.com } 23713531Sjairo.balart@metempsy.com } 23813531Sjairo.balart@metempsy.com 23913531Sjairo.balart@metempsy.com if (irqEnabled[int_id]) { 24013531Sjairo.balart@metempsy.com value |= (1 << int_id); 24113531Sjairo.balart@metempsy.com } 24213531Sjairo.balart@metempsy.com } 24313531Sjairo.balart@metempsy.com 24413531Sjairo.balart@metempsy.com return value; 24513531Sjairo.balart@metempsy.com } 24613531Sjairo.balart@metempsy.com 24713531Sjairo.balart@metempsy.com case GICR_ISPENDR0: // Interrupt Set-Pending Register 0 24813531Sjairo.balart@metempsy.com case GICR_ICPENDR0: { // Interrupt Clear-Pending Register 0 24913531Sjairo.balart@metempsy.com uint64_t value = 0; 25013531Sjairo.balart@metempsy.com 25113531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 25213531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 25313531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 25413531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 25513531Sjairo.balart@metempsy.com continue; 25613531Sjairo.balart@metempsy.com } 25713531Sjairo.balart@metempsy.com } 25813531Sjairo.balart@metempsy.com 25913531Sjairo.balart@metempsy.com value |= (irqPending[int_id] << int_id); 26013531Sjairo.balart@metempsy.com } 26113531Sjairo.balart@metempsy.com 26213531Sjairo.balart@metempsy.com return value; 26313531Sjairo.balart@metempsy.com } 26413531Sjairo.balart@metempsy.com 26513531Sjairo.balart@metempsy.com case GICR_ISACTIVER0: // Interrupt Set-Active Register 0 26613531Sjairo.balart@metempsy.com case GICR_ICACTIVER0: { // Interrupt Clear-Active Register 0 26713531Sjairo.balart@metempsy.com uint64_t value = 0; 26813531Sjairo.balart@metempsy.com 26913531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 27013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 27113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 27213531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 27313531Sjairo.balart@metempsy.com continue; 27413531Sjairo.balart@metempsy.com } 27513531Sjairo.balart@metempsy.com } 27613531Sjairo.balart@metempsy.com 27713531Sjairo.balart@metempsy.com value |= irqActive[int_id] << int_id; 27813531Sjairo.balart@metempsy.com } 27913531Sjairo.balart@metempsy.com 28013531Sjairo.balart@metempsy.com return value; 28113531Sjairo.balart@metempsy.com } 28213531Sjairo.balart@metempsy.com 28313531Sjairo.balart@metempsy.com case GICR_ICFGR0: // SGI Configuration Register 28413531Sjairo.balart@metempsy.com case GICR_ICFGR1: { // PPI Configuration Register 28513531Sjairo.balart@metempsy.com uint64_t value = 0; 28613531Sjairo.balart@metempsy.com uint32_t first_int_id = addr == GICR_ICFGR0 ? 0 : Gicv3::SGI_MAX; 28713531Sjairo.balart@metempsy.com 28813531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_int_id; i < 32; 28913756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 29013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 29113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 29213531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 29313531Sjairo.balart@metempsy.com continue; 29413531Sjairo.balart@metempsy.com } 29513531Sjairo.balart@metempsy.com } 29613531Sjairo.balart@metempsy.com 29713531Sjairo.balart@metempsy.com if (irqConfig[int_id] == Gicv3::INT_EDGE_TRIGGERED) { 29813531Sjairo.balart@metempsy.com value |= (0x2) << i; 29913531Sjairo.balart@metempsy.com } 30013531Sjairo.balart@metempsy.com } 30113531Sjairo.balart@metempsy.com 30213531Sjairo.balart@metempsy.com return value; 30313531Sjairo.balart@metempsy.com } 30413531Sjairo.balart@metempsy.com 30513531Sjairo.balart@metempsy.com case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0 30613531Sjairo.balart@metempsy.com uint64_t value = 0; 30713531Sjairo.balart@metempsy.com 30813531Sjairo.balart@metempsy.com if (distributor->DS) { 30913531Sjairo.balart@metempsy.com value = 0; 31013531Sjairo.balart@metempsy.com } else { 31113531Sjairo.balart@metempsy.com if (!is_secure_access) { 31213531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 31313531Sjairo.balart@metempsy.com value = 0; 31413531Sjairo.balart@metempsy.com } else { 31513531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 31613531Sjairo.balart@metempsy.com value |= irqGrpmod[int_id] << int_id; 31713531Sjairo.balart@metempsy.com } 31813531Sjairo.balart@metempsy.com } 31913531Sjairo.balart@metempsy.com } 32013531Sjairo.balart@metempsy.com 32113531Sjairo.balart@metempsy.com return value; 32213531Sjairo.balart@metempsy.com } 32313531Sjairo.balart@metempsy.com 32413531Sjairo.balart@metempsy.com case GICR_NSACR: { // Non-secure Access Control Register 32513531Sjairo.balart@metempsy.com uint64_t value = 0; 32613531Sjairo.balart@metempsy.com 32713531Sjairo.balart@metempsy.com if (distributor->DS) { 32813531Sjairo.balart@metempsy.com // RAZ/WI 32913531Sjairo.balart@metempsy.com value = 0; 33013531Sjairo.balart@metempsy.com } else { 33113531Sjairo.balart@metempsy.com if (!is_secure_access) { 33213531Sjairo.balart@metempsy.com // RAZ/WI 33313531Sjairo.balart@metempsy.com value = 0; 33413531Sjairo.balart@metempsy.com } else { 33513531Sjairo.balart@metempsy.com for (int i = 0, int_id = 0; i < 8 * size; 33613756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 33713531Sjairo.balart@metempsy.com value |= irqNsacr[int_id] << i; 33813531Sjairo.balart@metempsy.com } 33913531Sjairo.balart@metempsy.com } 34013531Sjairo.balart@metempsy.com } 34113531Sjairo.balart@metempsy.com 34213531Sjairo.balart@metempsy.com return value; 34313531Sjairo.balart@metempsy.com } 34413531Sjairo.balart@metempsy.com 34513690Sjairo.balart@metempsy.com case GICR_PROPBASER: // Redistributor Properties Base Address Register 34613690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 34713690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 34813690Sjairo.balart@metempsy.com // Physical_Address, bits [51:12] 34913690Sjairo.balart@metempsy.com // Bits [51:12] of the physical address containing the LPI 35013690Sjairo.balart@metempsy.com // Configuration table 35113690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 35213690Sjairo.balart@metempsy.com // 00 Non-shareable 35313690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 35413690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 35513690Sjairo.balart@metempsy.com // IDbits, bits [4:0] 35613690Sjairo.balart@metempsy.com // limited by GICD_TYPER.IDbits 35713690Sjairo.balart@metempsy.com return lpiConfigurationTablePtr | lpiIDBits; 35813690Sjairo.balart@metempsy.com 35913690Sjairo.balart@metempsy.com // Redistributor LPI Pending Table Base Address Register 36013690Sjairo.balart@metempsy.com case GICR_PENDBASER: 36113690Sjairo.balart@metempsy.com // PTZ, bit [62] 36213690Sjairo.balart@metempsy.com // Pending Table Zero 36313690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 36413690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 36513690Sjairo.balart@metempsy.com // Physical_Address, bits [51:16] 36613690Sjairo.balart@metempsy.com // Bits [51:16] of the physical address containing the LPI Pending 36713690Sjairo.balart@metempsy.com // table 36813690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 36913690Sjairo.balart@metempsy.com // 00 Non-shareable 37013690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 37113690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 37213690Sjairo.balart@metempsy.com return lpiPendingTablePtr; 37313690Sjairo.balart@metempsy.com 37413690Sjairo.balart@metempsy.com // Redistributor Synchronize Register 37513690Sjairo.balart@metempsy.com case GICR_SYNCR: 37613690Sjairo.balart@metempsy.com return 0; 37713690Sjairo.balart@metempsy.com 37813531Sjairo.balart@metempsy.com default: 37913531Sjairo.balart@metempsy.com panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr); 38013531Sjairo.balart@metempsy.com break; 38113531Sjairo.balart@metempsy.com } 38213531Sjairo.balart@metempsy.com} 38313531Sjairo.balart@metempsy.com 38413531Sjairo.balart@metempsy.comvoid 38513531Sjairo.balart@metempsy.comGicv3Redistributor::write(Addr addr, uint64_t data, size_t size, 38613531Sjairo.balart@metempsy.com bool is_secure_access) 38713531Sjairo.balart@metempsy.com{ 38813531Sjairo.balart@metempsy.com if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers 38913531Sjairo.balart@metempsy.com int first_intid = addr - GICR_IPRIORITYR.start(); 39013531Sjairo.balart@metempsy.com 39113531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < size; i++, int_id++) { 39213531Sjairo.balart@metempsy.com uint8_t prio = bits(data, (i + 1) * 8 - 1, (i * 8)); 39313531Sjairo.balart@metempsy.com 39413531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 39513531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 39613531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 39713531Sjairo.balart@metempsy.com continue; 39813531Sjairo.balart@metempsy.com } else { 39913531Sjairo.balart@metempsy.com // NS view 40013531Sjairo.balart@metempsy.com prio = 0x80 | (prio >> 1); 40113531Sjairo.balart@metempsy.com } 40213531Sjairo.balart@metempsy.com } 40313531Sjairo.balart@metempsy.com 40413531Sjairo.balart@metempsy.com irqPriority[int_id] = prio; 40513531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 40613531Sjairo.balart@metempsy.com "int_id %d priority %d\n", int_id, irqPriority[int_id]); 40713531Sjairo.balart@metempsy.com } 40813531Sjairo.balart@metempsy.com 40913531Sjairo.balart@metempsy.com return; 41013531Sjairo.balart@metempsy.com } 41113531Sjairo.balart@metempsy.com 41213531Sjairo.balart@metempsy.com switch (addr) { 41313531Sjairo.balart@metempsy.com case GICR_CTLR: { 41413690Sjairo.balart@metempsy.com // GICR_TYPER.LPIS is 0 so EnableLPIs is RES0 41513690Sjairo.balart@metempsy.com EnableLPIs = data & GICR_CTLR_ENABLE_LPIS; 41613531Sjairo.balart@metempsy.com DPG1S = data & GICR_CTLR_DPG1S; 41713531Sjairo.balart@metempsy.com DPG1NS = data & GICR_CTLR_DPG1NS; 41813531Sjairo.balart@metempsy.com DPG0 = data & GICR_CTLR_DPG0; 41913531Sjairo.balart@metempsy.com break; 42013531Sjairo.balart@metempsy.com } 42113531Sjairo.balart@metempsy.com 42213531Sjairo.balart@metempsy.com case GICR_WAKER: // Wake Register 42313531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 42413531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 42513531Sjairo.balart@metempsy.com return; 42613531Sjairo.balart@metempsy.com } 42713531Sjairo.balart@metempsy.com 42813531Sjairo.balart@metempsy.com if (not peInLowPowerState and 42913756Sjairo.balart@metempsy.com (data & GICR_WAKER_ProcessorSleep)) { 43013531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 43113531Sjairo.balart@metempsy.com "PE entering in low power state\n"); 43213531Sjairo.balart@metempsy.com } else if (peInLowPowerState and 43313756Sjairo.balart@metempsy.com not(data & GICR_WAKER_ProcessorSleep)) { 43413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): powering up PE\n"); 43513531Sjairo.balart@metempsy.com } 43613531Sjairo.balart@metempsy.com 43713531Sjairo.balart@metempsy.com peInLowPowerState = data & GICR_WAKER_ProcessorSleep; 43813531Sjairo.balart@metempsy.com break; 43913531Sjairo.balart@metempsy.com 44013531Sjairo.balart@metempsy.com case GICR_IGROUPR0: // Interrupt Group Register 0 44113531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 44213531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 44313531Sjairo.balart@metempsy.com return; 44413531Sjairo.balart@metempsy.com } 44513531Sjairo.balart@metempsy.com 44613531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 44713531Sjairo.balart@metempsy.com irqGroup[int_id] = data & (1 << int_id) ? 1 : 0; 44813531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 44913531Sjairo.balart@metempsy.com "int_id %d group %d\n", int_id, irqGroup[int_id]); 45013531Sjairo.balart@metempsy.com } 45113531Sjairo.balart@metempsy.com 45213531Sjairo.balart@metempsy.com break; 45313531Sjairo.balart@metempsy.com 45413531Sjairo.balart@metempsy.com case GICR_ISENABLER0: // Interrupt Set-Enable Register 0 45513531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 45613531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 45713531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 45813531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 45913531Sjairo.balart@metempsy.com continue; 46013531Sjairo.balart@metempsy.com } 46113531Sjairo.balart@metempsy.com } 46213531Sjairo.balart@metempsy.com 46313531Sjairo.balart@metempsy.com bool enable = data & (1 << int_id) ? 1 : 0; 46413531Sjairo.balart@metempsy.com 46513531Sjairo.balart@metempsy.com if (enable) { 46613531Sjairo.balart@metempsy.com irqEnabled[int_id] = true; 46713531Sjairo.balart@metempsy.com } 46813531Sjairo.balart@metempsy.com 46913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 47013531Sjairo.balart@metempsy.com "int_id %d enable %i\n", int_id, irqEnabled[int_id]); 47113531Sjairo.balart@metempsy.com } 47213531Sjairo.balart@metempsy.com 47313531Sjairo.balart@metempsy.com break; 47413531Sjairo.balart@metempsy.com 47513531Sjairo.balart@metempsy.com case GICR_ICENABLER0: // Interrupt Clear-Enable Register 0 47613531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 47713531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 47813531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 47913531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 48013531Sjairo.balart@metempsy.com continue; 48113531Sjairo.balart@metempsy.com } 48213531Sjairo.balart@metempsy.com } 48313531Sjairo.balart@metempsy.com 48413531Sjairo.balart@metempsy.com bool disable = data & (1 << int_id) ? 1 : 0; 48513531Sjairo.balart@metempsy.com 48613531Sjairo.balart@metempsy.com if (disable) { 48713531Sjairo.balart@metempsy.com irqEnabled[int_id] = false; 48813531Sjairo.balart@metempsy.com } 48913531Sjairo.balart@metempsy.com 49013531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 49113531Sjairo.balart@metempsy.com "int_id %d enable %i\n", int_id, irqEnabled[int_id]); 49213531Sjairo.balart@metempsy.com } 49313531Sjairo.balart@metempsy.com 49413531Sjairo.balart@metempsy.com break; 49513531Sjairo.balart@metempsy.com 49613531Sjairo.balart@metempsy.com case GICR_ISPENDR0: // Interrupt Set-Pending Register 0 49713531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 49813531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 49913531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 50013531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 50113531Sjairo.balart@metempsy.com continue; 50213531Sjairo.balart@metempsy.com } 50313531Sjairo.balart@metempsy.com } 50413531Sjairo.balart@metempsy.com 50513531Sjairo.balart@metempsy.com bool pending = data & (1 << int_id) ? 1 : 0; 50613531Sjairo.balart@metempsy.com 50713531Sjairo.balart@metempsy.com if (pending) { 50813531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write() " 50913531Sjairo.balart@metempsy.com "(GICR_ISPENDR0): int_id %d (PPI) " 51013531Sjairo.balart@metempsy.com "pending bit set\n", int_id); 51113531Sjairo.balart@metempsy.com irqPending[int_id] = true; 51213531Sjairo.balart@metempsy.com } 51313531Sjairo.balart@metempsy.com } 51413531Sjairo.balart@metempsy.com 51514231Sgiacomo.travaglini@arm.com updateDistributor(); 51613531Sjairo.balart@metempsy.com break; 51713531Sjairo.balart@metempsy.com 51813531Sjairo.balart@metempsy.com case GICR_ICPENDR0:// Interrupt Clear-Pending Register 0 51913531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 52013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 52113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 52213531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 52313531Sjairo.balart@metempsy.com continue; 52413531Sjairo.balart@metempsy.com } 52513531Sjairo.balart@metempsy.com } 52613531Sjairo.balart@metempsy.com 52713531Sjairo.balart@metempsy.com bool clear = data & (1 << int_id) ? 1 : 0; 52813531Sjairo.balart@metempsy.com 52913531Sjairo.balart@metempsy.com if (clear) { 53013531Sjairo.balart@metempsy.com irqPending[int_id] = false; 53113531Sjairo.balart@metempsy.com } 53213531Sjairo.balart@metempsy.com } 53313531Sjairo.balart@metempsy.com 53413531Sjairo.balart@metempsy.com break; 53513531Sjairo.balart@metempsy.com 53613531Sjairo.balart@metempsy.com case GICR_ISACTIVER0: // Interrupt Set-Active Register 0 53713531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 53813531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 53913531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 54013531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 54113531Sjairo.balart@metempsy.com continue; 54213531Sjairo.balart@metempsy.com } 54313531Sjairo.balart@metempsy.com } 54413531Sjairo.balart@metempsy.com 54513531Sjairo.balart@metempsy.com bool activate = data & (1 << int_id) ? 1 : 0; 54613531Sjairo.balart@metempsy.com 54713531Sjairo.balart@metempsy.com if (activate) { 54813531Sjairo.balart@metempsy.com if (!irqActive[int_id]) { 54913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 55013531Sjairo.balart@metempsy.com "int_id %d active set\n", int_id); 55113531Sjairo.balart@metempsy.com } 55213531Sjairo.balart@metempsy.com 55313531Sjairo.balart@metempsy.com irqActive[int_id] = true; 55413531Sjairo.balart@metempsy.com } 55513531Sjairo.balart@metempsy.com } 55613531Sjairo.balart@metempsy.com 55713531Sjairo.balart@metempsy.com break; 55813531Sjairo.balart@metempsy.com 55913531Sjairo.balart@metempsy.com case GICR_ICACTIVER0: // Interrupt Clear-Active Register 0 56013531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 56113531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 56213531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 56313531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 56413531Sjairo.balart@metempsy.com continue; 56513531Sjairo.balart@metempsy.com } 56613531Sjairo.balart@metempsy.com } 56713531Sjairo.balart@metempsy.com 56813531Sjairo.balart@metempsy.com bool clear = data & (1 << int_id) ? 1 : 0; 56913531Sjairo.balart@metempsy.com 57013531Sjairo.balart@metempsy.com if (clear) { 57113531Sjairo.balart@metempsy.com if (irqActive[int_id]) { 57213531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 57313531Sjairo.balart@metempsy.com "int_id %d active cleared\n", int_id); 57413531Sjairo.balart@metempsy.com } 57513531Sjairo.balart@metempsy.com 57613531Sjairo.balart@metempsy.com irqActive[int_id] = false; 57713531Sjairo.balart@metempsy.com } 57813531Sjairo.balart@metempsy.com } 57913531Sjairo.balart@metempsy.com 58013531Sjairo.balart@metempsy.com break; 58113531Sjairo.balart@metempsy.com 58213531Sjairo.balart@metempsy.com case GICR_ICFGR1: { // PPI Configuration Register 58313531Sjairo.balart@metempsy.com int first_intid = Gicv3::SGI_MAX; 58413531Sjairo.balart@metempsy.com 58513531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < 8 * size; 58613756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 58713531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 58813531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 58913531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 59013531Sjairo.balart@metempsy.com continue; 59113531Sjairo.balart@metempsy.com } 59213531Sjairo.balart@metempsy.com } 59313531Sjairo.balart@metempsy.com 59413756Sjairo.balart@metempsy.com irqConfig[int_id] = data & (0x2 << i) ? 59513756Sjairo.balart@metempsy.com Gicv3::INT_EDGE_TRIGGERED : 59613756Sjairo.balart@metempsy.com Gicv3::INT_LEVEL_SENSITIVE; 59713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 59813531Sjairo.balart@metempsy.com "int_id %d (PPI) config %d\n", 59913531Sjairo.balart@metempsy.com int_id, irqConfig[int_id]); 60013531Sjairo.balart@metempsy.com } 60113531Sjairo.balart@metempsy.com 60213531Sjairo.balart@metempsy.com break; 60313531Sjairo.balart@metempsy.com } 60413531Sjairo.balart@metempsy.com 60513531Sjairo.balart@metempsy.com case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0 60613531Sjairo.balart@metempsy.com if (distributor->DS) { 60713531Sjairo.balart@metempsy.com // RAZ/WI if secutiry disabled 60813531Sjairo.balart@metempsy.com } else { 60913531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 61013531Sjairo.balart@metempsy.com if (!is_secure_access) { 61113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 61213531Sjairo.balart@metempsy.com continue; 61313531Sjairo.balart@metempsy.com } 61413531Sjairo.balart@metempsy.com 61513531Sjairo.balart@metempsy.com irqGrpmod[int_id] = data & (1 << int_id); 61613531Sjairo.balart@metempsy.com } 61713531Sjairo.balart@metempsy.com } 61813531Sjairo.balart@metempsy.com 61913531Sjairo.balart@metempsy.com break; 62013531Sjairo.balart@metempsy.com } 62113531Sjairo.balart@metempsy.com 62213531Sjairo.balart@metempsy.com case GICR_NSACR: { // Non-secure Access Control Register 62313531Sjairo.balart@metempsy.com if (distributor->DS) { 62413531Sjairo.balart@metempsy.com // RAZ/WI 62513531Sjairo.balart@metempsy.com } else { 62613531Sjairo.balart@metempsy.com if (!is_secure_access) { 62713531Sjairo.balart@metempsy.com // RAZ/WI 62813531Sjairo.balart@metempsy.com } else { 62913531Sjairo.balart@metempsy.com for (int i = 0, int_id = 0; i < 8 * size; 63013756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 63113531Sjairo.balart@metempsy.com irqNsacr[int_id] = (data >> i) & 0x3; 63213531Sjairo.balart@metempsy.com } 63313531Sjairo.balart@metempsy.com } 63413531Sjairo.balart@metempsy.com } 63513531Sjairo.balart@metempsy.com 63613531Sjairo.balart@metempsy.com break; 63713531Sjairo.balart@metempsy.com } 63813531Sjairo.balart@metempsy.com 63913690Sjairo.balart@metempsy.com case GICR_SETLPIR: // Set LPI Pending Register 64013690Sjairo.balart@metempsy.com setClrLPI(data, true); 64113690Sjairo.balart@metempsy.com break; 64213690Sjairo.balart@metempsy.com 64313690Sjairo.balart@metempsy.com case GICR_CLRLPIR: // Clear LPI Pending Register 64413690Sjairo.balart@metempsy.com setClrLPI(data, false); 64513690Sjairo.balart@metempsy.com break; 64613690Sjairo.balart@metempsy.com 64713690Sjairo.balart@metempsy.com case GICR_PROPBASER: { // Redistributor Properties Base Address Register 64813690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 64913690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 65013690Sjairo.balart@metempsy.com // Physical_Address, bits [51:12] 65113690Sjairo.balart@metempsy.com // Bits [51:12] of the physical address containing the LPI 65213690Sjairo.balart@metempsy.com // Configuration table 65313690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 65413690Sjairo.balart@metempsy.com // 00 Non-shareable 65513690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 65613690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 65713690Sjairo.balart@metempsy.com // IDbits, bits [4:0] 65813690Sjairo.balart@metempsy.com // limited by GICD_TYPER.IDbits (= 0xf) 65913690Sjairo.balart@metempsy.com lpiConfigurationTablePtr = data & 0xFFFFFFFFFF000; 66013690Sjairo.balart@metempsy.com lpiIDBits = data & 0x1f; 66113690Sjairo.balart@metempsy.com 66213690Sjairo.balart@metempsy.com // 0xf here matches the value of GICD_TYPER.IDbits. 66313690Sjairo.balart@metempsy.com // TODO - make GICD_TYPER.IDbits a parameter instead of a hardcoded 66413690Sjairo.balart@metempsy.com // value 66513690Sjairo.balart@metempsy.com if (lpiIDBits > 0xf) { 66613690Sjairo.balart@metempsy.com lpiIDBits = 0xf; 66713690Sjairo.balart@metempsy.com } 66813690Sjairo.balart@metempsy.com 66913690Sjairo.balart@metempsy.com break; 67013690Sjairo.balart@metempsy.com } 67113690Sjairo.balart@metempsy.com 67213690Sjairo.balart@metempsy.com // Redistributor LPI Pending Table Base Address Register 67313690Sjairo.balart@metempsy.com case GICR_PENDBASER: 67413690Sjairo.balart@metempsy.com // PTZ, bit [62] 67513690Sjairo.balart@metempsy.com // Pending Table Zero 67613690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 67713690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 67813690Sjairo.balart@metempsy.com // Physical_Address, bits [51:16] 67913690Sjairo.balart@metempsy.com // Bits [51:16] of the physical address containing the LPI Pending 68013690Sjairo.balart@metempsy.com // table 68113690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 68213690Sjairo.balart@metempsy.com // 00 Non-shareable 68313690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 68413690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 68513690Sjairo.balart@metempsy.com lpiPendingTablePtr = data & 0xFFFFFFFFF0000; 68613690Sjairo.balart@metempsy.com break; 68713690Sjairo.balart@metempsy.com 68813690Sjairo.balart@metempsy.com case GICR_INVLPIR: { // Redistributor Invalidate LPI Register 68913921Sgiacomo.travaglini@arm.com // Do nothing: no caching supported 69013690Sjairo.balart@metempsy.com break; 69113690Sjairo.balart@metempsy.com } 69213690Sjairo.balart@metempsy.com 69313690Sjairo.balart@metempsy.com case GICR_INVALLR: { // Redistributor Invalidate All Register 69413921Sgiacomo.travaglini@arm.com // Do nothing: no caching supported 69513690Sjairo.balart@metempsy.com break; 69613690Sjairo.balart@metempsy.com } 69713690Sjairo.balart@metempsy.com 69813531Sjairo.balart@metempsy.com default: 69913531Sjairo.balart@metempsy.com panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr); 70013531Sjairo.balart@metempsy.com break; 70113531Sjairo.balart@metempsy.com } 70213531Sjairo.balart@metempsy.com} 70313531Sjairo.balart@metempsy.com 70413531Sjairo.balart@metempsy.comvoid 70513531Sjairo.balart@metempsy.comGicv3Redistributor::sendPPInt(uint32_t int_id) 70613531Sjairo.balart@metempsy.com{ 70713531Sjairo.balart@metempsy.com assert((int_id >= Gicv3::SGI_MAX) && 70813531Sjairo.balart@metempsy.com (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX)); 70913531Sjairo.balart@metempsy.com irqPending[int_id] = true; 71013531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): " 71113531Sjairo.balart@metempsy.com "int_id %d (PPI) pending bit set\n", int_id); 71214231Sgiacomo.travaglini@arm.com updateDistributor(); 71313531Sjairo.balart@metempsy.com} 71413531Sjairo.balart@metempsy.com 71513531Sjairo.balart@metempsy.comvoid 71613531Sjairo.balart@metempsy.comGicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns) 71713531Sjairo.balart@metempsy.com{ 71813531Sjairo.balart@metempsy.com assert(int_id < Gicv3::SGI_MAX); 71913531Sjairo.balart@metempsy.com Gicv3::GroupId int_group = getIntGroup(int_id); 72013531Sjairo.balart@metempsy.com 72114227Sgiacomo.travaglini@arm.com bool forward = false; 72214227Sgiacomo.travaglini@arm.com 72314227Sgiacomo.travaglini@arm.com if (ns) { 72414227Sgiacomo.travaglini@arm.com // Non-Secure EL1 and EL2 access 72514227Sgiacomo.travaglini@arm.com int nsaccess = irqNsacr[int_id]; 72614227Sgiacomo.travaglini@arm.com if (int_group == Gicv3::G0S) { 72714227Sgiacomo.travaglini@arm.com 72814227Sgiacomo.travaglini@arm.com forward = distributor->DS || (nsaccess >= 1); 72914227Sgiacomo.travaglini@arm.com 73014227Sgiacomo.travaglini@arm.com } else if (int_group == Gicv3::G1S) { 73114227Sgiacomo.travaglini@arm.com forward = ((group == Gicv3::G1S || group == Gicv3::G1NS ) && 73214227Sgiacomo.travaglini@arm.com nsaccess == 2); 73314227Sgiacomo.travaglini@arm.com } else { 73414227Sgiacomo.travaglini@arm.com // G1NS 73514227Sgiacomo.travaglini@arm.com forward = group == Gicv3::G1NS; 73614227Sgiacomo.travaglini@arm.com } 73714227Sgiacomo.travaglini@arm.com } else { 73814227Sgiacomo.travaglini@arm.com // Secure EL1 and EL3 access 73914227Sgiacomo.travaglini@arm.com forward = (group == int_group) || 74014227Sgiacomo.travaglini@arm.com (group == Gicv3::G1S && int_group == Gicv3::G0S && 74114227Sgiacomo.travaglini@arm.com distributor->DS); 74213531Sjairo.balart@metempsy.com } 74313531Sjairo.balart@metempsy.com 74414227Sgiacomo.travaglini@arm.com if (!forward) return; 74513531Sjairo.balart@metempsy.com 74613531Sjairo.balart@metempsy.com irqPending[int_id] = true; 74713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3ReDistributor::sendSGI(): " 74813531Sjairo.balart@metempsy.com "int_id %d (SGI) pending bit set\n", int_id); 74914231Sgiacomo.travaglini@arm.com updateDistributor(); 75013531Sjairo.balart@metempsy.com} 75113531Sjairo.balart@metempsy.com 75213531Sjairo.balart@metempsy.comGicv3::IntStatus 75313756Sjairo.balart@metempsy.comGicv3Redistributor::intStatus(uint32_t int_id) const 75413531Sjairo.balart@metempsy.com{ 75513531Sjairo.balart@metempsy.com assert(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX); 75613531Sjairo.balart@metempsy.com 75713531Sjairo.balart@metempsy.com if (irqPending[int_id]) { 75813531Sjairo.balart@metempsy.com if (irqActive[int_id]) { 75913531Sjairo.balart@metempsy.com return Gicv3::INT_ACTIVE_PENDING; 76013531Sjairo.balart@metempsy.com } 76113531Sjairo.balart@metempsy.com 76213531Sjairo.balart@metempsy.com return Gicv3::INT_PENDING; 76313531Sjairo.balart@metempsy.com } else if (irqActive[int_id]) { 76413531Sjairo.balart@metempsy.com return Gicv3::INT_ACTIVE; 76513531Sjairo.balart@metempsy.com } else { 76613531Sjairo.balart@metempsy.com return Gicv3::INT_INACTIVE; 76713531Sjairo.balart@metempsy.com } 76813531Sjairo.balart@metempsy.com} 76913531Sjairo.balart@metempsy.com 77014231Sgiacomo.travaglini@arm.comvoid 77114231Sgiacomo.travaglini@arm.comGicv3Redistributor::updateDistributor() 77214231Sgiacomo.travaglini@arm.com{ 77314231Sgiacomo.travaglini@arm.com distributor->update(); 77414231Sgiacomo.travaglini@arm.com} 77514231Sgiacomo.travaglini@arm.com 77613531Sjairo.balart@metempsy.com/* 77713531Sjairo.balart@metempsy.com * Recalculate the highest priority pending interrupt after a 77813531Sjairo.balart@metempsy.com * change to redistributor state. 77913531Sjairo.balart@metempsy.com */ 78013531Sjairo.balart@metempsy.comvoid 78113531Sjairo.balart@metempsy.comGicv3Redistributor::update() 78213531Sjairo.balart@metempsy.com{ 78313531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id++) { 78413531Sjairo.balart@metempsy.com Gicv3::GroupId int_group = getIntGroup(int_id); 78513531Sjairo.balart@metempsy.com bool group_enabled = distributor->groupEnabled(int_group); 78613531Sjairo.balart@metempsy.com 78713531Sjairo.balart@metempsy.com if (irqPending[int_id] && irqEnabled[int_id] && 78813531Sjairo.balart@metempsy.com !irqActive[int_id] && group_enabled) { 78913531Sjairo.balart@metempsy.com if ((irqPriority[int_id] < cpuInterface->hppi.prio) || 79013756Sjairo.balart@metempsy.com /* 79113756Sjairo.balart@metempsy.com * Multiple pending ints with same priority. 79213756Sjairo.balart@metempsy.com * Implementation choice which one to signal. 79313756Sjairo.balart@metempsy.com * Our implementation selects the one with the lower id. 79413756Sjairo.balart@metempsy.com */ 79513756Sjairo.balart@metempsy.com (irqPriority[int_id] == cpuInterface->hppi.prio && 79613756Sjairo.balart@metempsy.com int_id < cpuInterface->hppi.intid)) { 79713531Sjairo.balart@metempsy.com cpuInterface->hppi.intid = int_id; 79813531Sjairo.balart@metempsy.com cpuInterface->hppi.prio = irqPriority[int_id]; 79913531Sjairo.balart@metempsy.com cpuInterface->hppi.group = int_group; 80013531Sjairo.balart@metempsy.com } 80113531Sjairo.balart@metempsy.com } 80213531Sjairo.balart@metempsy.com } 80313531Sjairo.balart@metempsy.com 80413690Sjairo.balart@metempsy.com // Check LPIs 80513920Sgiacomo.travaglini@arm.com if (EnableLPIs) { 80613921Sgiacomo.travaglini@arm.com 80713920Sgiacomo.travaglini@arm.com const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1); 80813921Sgiacomo.travaglini@arm.com const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1; 80913921Sgiacomo.travaglini@arm.com 81013921Sgiacomo.travaglini@arm.com uint8_t lpi_pending_table[largest_lpi_id / 8]; 81113921Sgiacomo.travaglini@arm.com uint8_t lpi_config_table[number_lpis]; 81213921Sgiacomo.travaglini@arm.com 81313928Sgiacomo.travaglini@arm.com memProxy->readBlob(lpiPendingTablePtr, 81414010Sgabeblack@google.com lpi_pending_table, 81513928Sgiacomo.travaglini@arm.com sizeof(lpi_pending_table)); 81613919Sgiacomo.travaglini@arm.com 81713928Sgiacomo.travaglini@arm.com memProxy->readBlob(lpiConfigurationTablePtr, 81814010Sgabeblack@google.com lpi_config_table, 81913928Sgiacomo.travaglini@arm.com sizeof(lpi_config_table)); 82013921Sgiacomo.travaglini@arm.com 82113920Sgiacomo.travaglini@arm.com for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id; 82213920Sgiacomo.travaglini@arm.com lpi_id++) { 82313920Sgiacomo.travaglini@arm.com uint32_t lpi_pending_entry_byte = lpi_id / 8; 82413920Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry_bit_position = lpi_id % 8; 82513920Sgiacomo.travaglini@arm.com bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] & 82613920Sgiacomo.travaglini@arm.com 1 << lpi_pending_entry_bit_position; 82713920Sgiacomo.travaglini@arm.com uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID; 82813921Sgiacomo.travaglini@arm.com 82913921Sgiacomo.travaglini@arm.com LPIConfigurationTableEntry config_entry = 83013921Sgiacomo.travaglini@arm.com lpi_config_table[lpi_configuration_entry_index]; 83113921Sgiacomo.travaglini@arm.com 83213921Sgiacomo.travaglini@arm.com bool lpi_is_enable = config_entry.enable; 83313921Sgiacomo.travaglini@arm.com 83413920Sgiacomo.travaglini@arm.com // LPIs are always Non-secure Group 1 interrupts, 83513920Sgiacomo.travaglini@arm.com // in a system where two Security states are enabled. 83613920Sgiacomo.travaglini@arm.com Gicv3::GroupId lpi_group = Gicv3::G1NS; 83713920Sgiacomo.travaglini@arm.com bool group_enabled = distributor->groupEnabled(lpi_group); 83813690Sjairo.balart@metempsy.com 83913920Sgiacomo.travaglini@arm.com if (lpi_is_pending && lpi_is_enable && group_enabled) { 84013922Sgiacomo.travaglini@arm.com uint8_t lpi_priority = config_entry.priority << 2; 84113690Sjairo.balart@metempsy.com 84213920Sgiacomo.travaglini@arm.com if ((lpi_priority < cpuInterface->hppi.prio) || 84313920Sgiacomo.travaglini@arm.com (lpi_priority == cpuInterface->hppi.prio && 84413920Sgiacomo.travaglini@arm.com lpi_id < cpuInterface->hppi.intid)) { 84513920Sgiacomo.travaglini@arm.com cpuInterface->hppi.intid = lpi_id; 84613920Sgiacomo.travaglini@arm.com cpuInterface->hppi.prio = lpi_priority; 84713920Sgiacomo.travaglini@arm.com cpuInterface->hppi.group = lpi_group; 84813920Sgiacomo.travaglini@arm.com } 84913690Sjairo.balart@metempsy.com } 85013690Sjairo.balart@metempsy.com } 85113690Sjairo.balart@metempsy.com } 85213690Sjairo.balart@metempsy.com 85314231Sgiacomo.travaglini@arm.com cpuInterface->update(); 85413531Sjairo.balart@metempsy.com} 85513531Sjairo.balart@metempsy.com 85613924Sgiacomo.travaglini@arm.comuint8_t 85713924Sgiacomo.travaglini@arm.comGicv3Redistributor::readEntryLPI(uint32_t lpi_id) 85813924Sgiacomo.travaglini@arm.com{ 85913924Sgiacomo.travaglini@arm.com Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8); 86013924Sgiacomo.travaglini@arm.com 86113924Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry; 86213928Sgiacomo.travaglini@arm.com memProxy->readBlob(lpi_pending_entry_ptr, 86314010Sgabeblack@google.com &lpi_pending_entry, 86413928Sgiacomo.travaglini@arm.com sizeof(lpi_pending_entry)); 86513924Sgiacomo.travaglini@arm.com 86613924Sgiacomo.travaglini@arm.com return lpi_pending_entry; 86713924Sgiacomo.travaglini@arm.com} 86813924Sgiacomo.travaglini@arm.com 86913924Sgiacomo.travaglini@arm.comvoid 87013924Sgiacomo.travaglini@arm.comGicv3Redistributor::writeEntryLPI(uint32_t lpi_id, uint8_t lpi_pending_entry) 87113924Sgiacomo.travaglini@arm.com{ 87213924Sgiacomo.travaglini@arm.com Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8); 87313924Sgiacomo.travaglini@arm.com 87413928Sgiacomo.travaglini@arm.com memProxy->writeBlob(lpi_pending_entry_ptr, 87514010Sgabeblack@google.com &lpi_pending_entry, 87613928Sgiacomo.travaglini@arm.com sizeof(lpi_pending_entry)); 87713924Sgiacomo.travaglini@arm.com} 87813924Sgiacomo.travaglini@arm.com 87913924Sgiacomo.travaglini@arm.combool 88013924Sgiacomo.travaglini@arm.comGicv3Redistributor::isPendingLPI(uint32_t lpi_id) 88113924Sgiacomo.travaglini@arm.com{ 88213924Sgiacomo.travaglini@arm.com // Fetch the LPI pending entry from memory 88313924Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry = readEntryLPI(lpi_id); 88413924Sgiacomo.travaglini@arm.com 88513924Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry_bit_position = lpi_id % 8; 88613924Sgiacomo.travaglini@arm.com bool is_set = lpi_pending_entry & (1 << lpi_pending_entry_bit_position); 88713924Sgiacomo.travaglini@arm.com 88813924Sgiacomo.travaglini@arm.com return is_set; 88913924Sgiacomo.travaglini@arm.com} 89013924Sgiacomo.travaglini@arm.com 89113531Sjairo.balart@metempsy.comvoid 89213690Sjairo.balart@metempsy.comGicv3Redistributor::setClrLPI(uint64_t data, bool set) 89313690Sjairo.balart@metempsy.com{ 89413690Sjairo.balart@metempsy.com if (!EnableLPIs) { 89513690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if 89613690Sjairo.balart@metempsy.com // GICR_CTLR.EnableLPIs == 0. 89713690Sjairo.balart@metempsy.com return; 89813690Sjairo.balart@metempsy.com } 89913690Sjairo.balart@metempsy.com 90013690Sjairo.balart@metempsy.com uint32_t lpi_id = data & 0xffffffff; 90113917Sgiacomo.travaglini@arm.com uint32_t largest_lpi_id = 1 << (lpiIDBits + 1); 90213690Sjairo.balart@metempsy.com 90313690Sjairo.balart@metempsy.com if (lpi_id > largest_lpi_id) { 90413690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if 90513690Sjairo.balart@metempsy.com // pINTID value specifies an unimplemented LPI. 90613690Sjairo.balart@metempsy.com return; 90713690Sjairo.balart@metempsy.com } 90813690Sjairo.balart@metempsy.com 90913924Sgiacomo.travaglini@arm.com // Fetch the LPI pending entry from memory 91013924Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry = readEntryLPI(lpi_id); 91113924Sgiacomo.travaglini@arm.com 91213690Sjairo.balart@metempsy.com uint8_t lpi_pending_entry_bit_position = lpi_id % 8; 91313690Sjairo.balart@metempsy.com bool is_set = lpi_pending_entry & (1 << lpi_pending_entry_bit_position); 91413690Sjairo.balart@metempsy.com 91513690Sjairo.balart@metempsy.com if (set) { 91613690Sjairo.balart@metempsy.com if (is_set) { 91713690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR have not effect if the pINTID field 91813690Sjairo.balart@metempsy.com // corresponds to an LPI that is already pending. 91913690Sjairo.balart@metempsy.com return; 92013690Sjairo.balart@metempsy.com } 92113690Sjairo.balart@metempsy.com 92213690Sjairo.balart@metempsy.com lpi_pending_entry |= 1 << (lpi_pending_entry_bit_position); 92313690Sjairo.balart@metempsy.com } else { 92413690Sjairo.balart@metempsy.com if (!is_set) { 92513690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR have not effect if the pINTID field 92613690Sjairo.balart@metempsy.com // corresponds to an LPI that is not pending. 92713690Sjairo.balart@metempsy.com return; 92813690Sjairo.balart@metempsy.com } 92913690Sjairo.balart@metempsy.com 93013690Sjairo.balart@metempsy.com lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position)); 93114260Sgiacomo.travaglini@arm.com 93214260Sgiacomo.travaglini@arm.com // Remove the pending state from the cpu interface 93314260Sgiacomo.travaglini@arm.com cpuInterface->resetHppi(lpi_id); 93413690Sjairo.balart@metempsy.com } 93513690Sjairo.balart@metempsy.com 93613924Sgiacomo.travaglini@arm.com writeEntryLPI(lpi_id, lpi_pending_entry); 93713924Sgiacomo.travaglini@arm.com 93814231Sgiacomo.travaglini@arm.com updateDistributor(); 93913531Sjairo.balart@metempsy.com} 94013531Sjairo.balart@metempsy.com 94113531Sjairo.balart@metempsy.comGicv3::GroupId 94213756Sjairo.balart@metempsy.comGicv3Redistributor::getIntGroup(int int_id) const 94313531Sjairo.balart@metempsy.com{ 94413531Sjairo.balart@metempsy.com assert(int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX)); 94513531Sjairo.balart@metempsy.com 94613531Sjairo.balart@metempsy.com if (distributor->DS) { 94713531Sjairo.balart@metempsy.com if (irqGroup[int_id] == 0) { 94813531Sjairo.balart@metempsy.com return Gicv3::G0S; 94913531Sjairo.balart@metempsy.com } else { 95013531Sjairo.balart@metempsy.com return Gicv3::G1NS; 95113531Sjairo.balart@metempsy.com } 95213531Sjairo.balart@metempsy.com } else { 95313531Sjairo.balart@metempsy.com if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 0) { 95413531Sjairo.balart@metempsy.com return Gicv3::G0S; 95513531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 1) { 95613531Sjairo.balart@metempsy.com return Gicv3::G1NS; 95713531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 0) { 95813531Sjairo.balart@metempsy.com return Gicv3::G1S; 95913531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 1) { 96013531Sjairo.balart@metempsy.com return Gicv3::G1NS; 96113531Sjairo.balart@metempsy.com } 96213531Sjairo.balart@metempsy.com } 96313531Sjairo.balart@metempsy.com 96413531Sjairo.balart@metempsy.com M5_UNREACHABLE; 96513531Sjairo.balart@metempsy.com} 96613531Sjairo.balart@metempsy.com 96713531Sjairo.balart@metempsy.comvoid 96813531Sjairo.balart@metempsy.comGicv3Redistributor::activateIRQ(uint32_t int_id) 96913531Sjairo.balart@metempsy.com{ 97013531Sjairo.balart@metempsy.com irqPending[int_id] = false; 97113531Sjairo.balart@metempsy.com irqActive[int_id] = true; 97213531Sjairo.balart@metempsy.com} 97313531Sjairo.balart@metempsy.com 97413531Sjairo.balart@metempsy.comvoid 97513531Sjairo.balart@metempsy.comGicv3Redistributor::deactivateIRQ(uint32_t int_id) 97613531Sjairo.balart@metempsy.com{ 97713531Sjairo.balart@metempsy.com irqActive[int_id] = false; 97813531Sjairo.balart@metempsy.com} 97913531Sjairo.balart@metempsy.com 98013531Sjairo.balart@metempsy.comuint32_t 98113756Sjairo.balart@metempsy.comGicv3Redistributor::getAffinity() const 98213531Sjairo.balart@metempsy.com{ 98313531Sjairo.balart@metempsy.com ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId); 98413531Sjairo.balart@metempsy.com uint64_t mpidr = getMPIDR(gic->getSystem(), tc); 98513531Sjairo.balart@metempsy.com /* 98613531Sjairo.balart@metempsy.com * Aff3 = MPIDR[39:32] 98713531Sjairo.balart@metempsy.com * (Note getMPIDR() returns uint32_t so Aff3 is always 0...) 98813531Sjairo.balart@metempsy.com * Aff2 = MPIDR[23:16] 98913531Sjairo.balart@metempsy.com * Aff1 = MPIDR[15:8] 99013531Sjairo.balart@metempsy.com * Aff0 = MPIDR[7:0] 99113531Sjairo.balart@metempsy.com * affinity = Aff3.Aff2.Aff1.Aff0 99213531Sjairo.balart@metempsy.com */ 99313531Sjairo.balart@metempsy.com uint64_t affinity = ((mpidr & 0xff00000000) >> 8) | (mpidr & (0xffffff)); 99413531Sjairo.balart@metempsy.com return affinity; 99513531Sjairo.balart@metempsy.com} 99613531Sjairo.balart@metempsy.com 99713531Sjairo.balart@metempsy.combool 99813756Sjairo.balart@metempsy.comGicv3Redistributor::canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const 99913531Sjairo.balart@metempsy.com{ 100013531Sjairo.balart@metempsy.com if (peInLowPowerState) { 100113531Sjairo.balart@metempsy.com return false; 100213531Sjairo.balart@metempsy.com } 100313531Sjairo.balart@metempsy.com 100413531Sjairo.balart@metempsy.com if (!distributor->groupEnabled(group)) { 100513531Sjairo.balart@metempsy.com return false; 100613531Sjairo.balart@metempsy.com } 100713531Sjairo.balart@metempsy.com 100813531Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && DPG1S) { 100913531Sjairo.balart@metempsy.com return false; 101013531Sjairo.balart@metempsy.com } 101113531Sjairo.balart@metempsy.com 101213531Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && DPG1NS) { 101313531Sjairo.balart@metempsy.com return false; 101413531Sjairo.balart@metempsy.com } 101513531Sjairo.balart@metempsy.com 101613531Sjairo.balart@metempsy.com if ((group == Gicv3::G0S) && DPG0) { 101713531Sjairo.balart@metempsy.com return false; 101813531Sjairo.balart@metempsy.com } 101913531Sjairo.balart@metempsy.com 102013531Sjairo.balart@metempsy.com return true; 102113531Sjairo.balart@metempsy.com} 102213531Sjairo.balart@metempsy.com 102313531Sjairo.balart@metempsy.comvoid 102413531Sjairo.balart@metempsy.comGicv3Redistributor::serialize(CheckpointOut & cp) const 102513531Sjairo.balart@metempsy.com{ 102613531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(peInLowPowerState); 102713531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqGroup); 102813531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqEnabled); 102913531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqPending); 103013531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqActive); 103113531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqPriority); 103213531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqConfig); 103313531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqGrpmod); 103413531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqNsacr); 103513531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG1S); 103613531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG1NS); 103713531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG0); 103813690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(EnableLPIs); 103913690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiConfigurationTablePtr); 104013690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiIDBits); 104113690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiPendingTablePtr); 104213531Sjairo.balart@metempsy.com} 104313531Sjairo.balart@metempsy.com 104413531Sjairo.balart@metempsy.comvoid 104513531Sjairo.balart@metempsy.comGicv3Redistributor::unserialize(CheckpointIn & cp) 104613531Sjairo.balart@metempsy.com{ 104713531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(peInLowPowerState); 104813531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqGroup); 104913531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqEnabled); 105013531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqPending); 105113531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqActive); 105213531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqPriority); 105313531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqConfig); 105413531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqGrpmod); 105513531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqNsacr); 105613531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG1S); 105713531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG1NS); 105813531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG0); 105913690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(EnableLPIs); 106013690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiConfigurationTablePtr); 106113690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiIDBits); 106213690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiPendingTablePtr); 106313531Sjairo.balart@metempsy.com} 1064