| /gem5/src/mem/ruby/structures/ |
| H A D | DirectoryMemory.py | 50 addr_ranges = VectorParam.AddrRange( variable in class:RubyDirectoryMemory
51 Parent.addr_ranges, "Address range this directory responds to")
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| H A D | DirectoryMemory.cc | 57 : SimObject(p), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
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| /gem5/src/mem/ |
| H A D | ExternalSlave.py | 47 addr_ranges = VectorParam.AddrRange([], 'Addresses served by' variable in class:ExternalSlave
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| H A D | external_slave.cc | 189 addrRanges(params->addr_ranges.begin(), params->addr_ranges.end())
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | Controller.py | 52 addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this " variable in class:RubyController
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| H A D | AbstractController.cc | 60 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
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| /gem5/util/tlm/conf/ |
| H A D | tlm_slave.py | 65 system.tlm.addr_ranges = [AddrRange('512MB')]
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| H A D | tlm_elastic_slave.py | 108 system.tlm.addr_ranges = [AddrRange('512MB')]
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | TlmBridge.py | 43 addr_ranges = VectorParam.AddrRange([], variable in class:Gem5ToTlmBridgeBase
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| H A D | gem5_to_tlm.cc | 469 addrRanges(params->addr_ranges.begin(), params->addr_ranges.end())
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| /gem5/configs/common/ |
| H A D | MemConfig.py | 184 addr_ranges=system.mem_ranges)
192 addr_ranges=system.mem_ranges)
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| H A D | CacheConfig.py | 225 addr_ranges=[AllMemory])
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| H A D | FSConfig.py | 357 addr_ranges=self.mem_ranges)
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| /gem5/util/tlm/examples/ |
| H A D | tlm_elastic_slave_with_l2.py | 116 system.tlm.addr_ranges = [AddrRange('4096MB')]
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| /gem5/src/mem/cache/ |
| H A D | Cache.py | 116 addr_ranges = VectorParam.AddrRange([AllMemory], variable in class:BaseCache
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| H A D | base.cc | 109 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
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| /gem5/configs/ruby/ |
| H A D | Ruby.py | 139 dir_cntrl.addr_ranges = dir_ranges
246 rom_dir_cntrl.addr_ranges = bootmem.range
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| H A D | MOESI_CMP_directory.py | 170 addr_ranges = l2_addr_ranges[i])
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| H A D | MOESI_AMD_Base.py | 176 self.addr_ranges = dir_ranges
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| H A D | GPU_RfO.py | 380 self.addr_ranges = dir_ranges
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| /gem5/tests/configs/ |
| H A D | base_config.py | 281 system.llc = [NoncoherentCache(addr_ranges = [r],
296 system.iocache = IOCache(addr_ranges=system.mem_ranges)
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| /gem5/configs/learning_gem5/part3/ |
| H A D | msi_caches.py | 200 self.addr_ranges = ranges
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| H A D | ruby_caches_MI_example.py | 189 self.addr_ranges = ranges
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| /gem5/configs/example/arm/ |
| H A D | devices.py | 221 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
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| /gem5/configs/example/ |
| H A D | fs.py | 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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