Searched refs:_addr (Results 1 - 20 of 20) sorted by relevance

/gem5/src/dev/i2c/
H A Ddevice.hh57 uint8_t _addr; member in class:I2CDevice
62 : SimObject(p), _addr(p->i2c_addr)
92 uint8_t i2cAddr() const { return _addr; }
/gem5/src/sim/
H A Dsyscall_emul_buf.hh64 BaseBufferArg(Addr _addr, int _size) argument
65 : addr(_addr), size(_size), bufPtr(new uint8_t[size])
112 BufferArg(Addr _addr, int _size) : BaseBufferArg(_addr, _size) { } argument
139 TypedBufferArg(Addr _addr, int _size = sizeof(T)) argument
140 : BaseBufferArg(_addr, _size)
/gem5/src/arch/arm/
H A Dtlbi_op.hh184 Addr _addr)
185 : TLBIOp(_targetEL, _secure), addr(_addr)
199 Addr _addr, uint16_t _asid)
200 : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
215 Addr _addr, uint16_t _asid)
216 : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
233 Addr _addr, uint16_t _asid)
234 : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
250 TLBIIPA(ExceptionLevel _targetEL, bool _secure, Addr _addr) argument
251 : TLBIOp(_targetEL, _secure), addr(_addr)
183 TLBIMVAA(ExceptionLevel _targetEL, bool _secure, Addr _addr) argument
198 TLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid) argument
214 ITLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid) argument
232 DTLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid) argument
[all...]
H A Dfaults.hh463 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, argument
465 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
490 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, argument
492 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
512 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, argument
514 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
/gem5/src/arch/arm/tracers/
H A Dtarmac_base.cc92 Addr _addr,
94 : size(_size), addr(_addr), data(_data)
90 MemEntry( uint8_t _size, Addr _addr, uint64_t _data) argument
H A Dtarmac_record_v8.cc65 uint8_t _size, Addr _addr, uint64_t _data)
66 : TraceMemEntry(tarmCtx, _size, _addr, _data),
68 paddr(_addr)
63 TraceMemEntryV8( const TarmacContext& tarmCtx, uint8_t _size, Addr _addr, uint64_t _data) argument
H A Dtarmac_base.hh117 MemEntry(uint8_t _size, Addr _addr, uint64_t _data);
H A Dtarmac_record_v8.hh121 uint8_t _size, Addr _addr, uint64_t _data);
H A Dtarmac_record.cc145 uint8_t _size, Addr _addr, uint64_t _data)
146 : MemEntry(_size, _addr, _data),
143 TraceMemEntry( const TarmacContext& tarmCtx, uint8_t _size, Addr _addr, uint64_t _data) argument
H A Dtarmac_record.hh168 uint8_t _size, Addr _addr, uint64_t _data);
/gem5/src/arch/riscv/
H A Dfaults.hh202 const Addr _addr; member in class:RiscvISA::AddressFault
206 : RiscvFault("Address", false, code), _addr(addr)
209 RegVal trap_value() const override { return _addr; }
/gem5/src/mem/
H A Dabstract_mem.hh96 LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid) argument
H A Ddram_ctrl.hh735 uint32_t _row, uint16_t bank_id, Addr _addr,
740 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
734 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr, unsigned int _size, Bank& bank_ref, Rank& rank_ref) argument
H A Dpacket.hh736 void setAddr(Addr _addr) { assert(flags.isSet(VALID_ADDR)); addr = _addr; } argument
/gem5/src/arch/x86/
H A Dfaults.hh318 PageFault(Addr _addr, uint32_t _errorCode) : argument
319 X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
322 PageFault(Addr _addr, bool present, BaseTLB::Mode mode, argument
324 X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
/gem5/src/mem/cache/
H A Dcache_blk.hh448 Addr _addr; member in class:final
469 _addr = MaxAddr;
479 _addr = addr;
497 return _addr;
/gem5/src/cpu/o3/
H A Dlsq.hh297 const Addr _addr; variable
308 _res(nullptr), _addr(0), _size(0), _flags(0),
326 _res(res), _addr(addr), _size(size),
695 using LSQRequest::_addr;
748 using LSQRequest::_addr;
H A Dlsq_impl.hh859 this->addRequest(_addr, _size, _byteEnable);
894 Addr base_addr = _addr;
895 Addr next_addr = addrBlockAlign(_addr + cacheLineSize, cacheLineSize);
896 Addr final_addr = addrBlockAlign(_addr + _size, cacheLineSize);
1047 Addr base_address = _addr;
/gem5/src/gpu-compute/
H A Dgpu_tlb.hh394 TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome,
H A Dgpu_tlb.cc1113 GpuTLB::TLBEvent::TLBEvent(GpuTLB* _tlb, Addr _addr, tlbOutcome tlb_outcome, argument
1115 : Event(CPU_Tick_Pri), tlb(_tlb), virtPageAddr(_addr),

Completed in 50 milliseconds