16019Shines@cs.fsu.edu/*
214128Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
37189Sgblack@eecs.umich.edu * All rights reserved
47189Sgblack@eecs.umich.edu *
57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall
67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual
77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating
87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software
97189Sgblack@eecs.umich.edu * licensed hereunder.  You may use the software subject to the license
107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated
117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software,
127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form.
137189Sgblack@eecs.umich.edu *
146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University
166019Shines@cs.fsu.edu * All rights reserved.
176019Shines@cs.fsu.edu *
186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
276019Shines@cs.fsu.edu * this software without specific prior written permission.
286019Shines@cs.fsu.edu *
296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019Shines@cs.fsu.edu *
416735Sgblack@eecs.umich.edu * Authors: Ali Saidi
426735Sgblack@eecs.umich.edu *          Gabe Black
4310037SARM gem5 Developers *          Giacomo Gabrielli
4410037SARM gem5 Developers *          Thomas Grocutt
456019Shines@cs.fsu.edu */
466019Shines@cs.fsu.edu
476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__
486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__
496019Shines@cs.fsu.edu
507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh"
5110037SARM gem5 Developers#include "arch/arm/pagetable.hh"
526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh"
5312334Sgabeblack@google.com#include "base/logging.hh"
546019Shines@cs.fsu.edu#include "sim/faults.hh"
558782Sgblack@eecs.umich.edu#include "sim/full_system.hh"
566019Shines@cs.fsu.edu
576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh
586019Shines@cs.fsu.edu
596019Shines@cs.fsu.edunamespace ArmISA
606019Shines@cs.fsu.edu{
6111294Sandreas.hansson@arm.comtypedef Addr FaultOffset;
626019Shines@cs.fsu.edu
6313896Sgiacomo.travaglini@arm.comclass ArmStaticInst;
6413896Sgiacomo.travaglini@arm.com
657362Sgblack@eecs.umich.educlass ArmFault : public FaultBase
666019Shines@cs.fsu.edu{
676019Shines@cs.fsu.edu  protected:
6810037SARM gem5 Developers    ExtMachInst machInst;
6910037SARM gem5 Developers    uint32_t issRaw;
7010037SARM gem5 Developers
7110037SARM gem5 Developers    // Helper variables for ARMv8 exception handling
7210037SARM gem5 Developers    bool from64;  // True if the exception is generated from the AArch64 state
7310037SARM gem5 Developers    bool to64;  // True if the exception is taken in AArch64 state
7410037SARM gem5 Developers    ExceptionLevel fromEL;  // Source exception level
7510037SARM gem5 Developers    ExceptionLevel toEL;  // Target exception level
7612569Sgiacomo.travaglini@arm.com    OperatingMode fromMode;  // Source operating mode (aarch32)
7712569Sgiacomo.travaglini@arm.com    OperatingMode toMode;  // Next operating mode (aarch32)
7812569Sgiacomo.travaglini@arm.com
7912569Sgiacomo.travaglini@arm.com    // This variable is true if the above fault specific informations
8012569Sgiacomo.travaglini@arm.com    // have been updated. This is to prevent that a client is using their
8112569Sgiacomo.travaglini@arm.com    // un-updated default constructed value.
8212569Sgiacomo.travaglini@arm.com    bool faultUpdated;
8310037SARM gem5 Developers
8412402Sgiacomo.travaglini@arm.com    bool hypRouted; // True if the fault has been routed to Hypervisor
8514128Sgiacomo.travaglini@arm.com    bool span; // True if the fault is setting the PSTATE.PAN bit
8612402Sgiacomo.travaglini@arm.com
8713396Sgiacomo.travaglini@arm.com    virtual Addr getVector(ThreadContext *tc);
8810037SARM gem5 Developers    Addr getVector64(ThreadContext *tc);
896735Sgblack@eecs.umich.edu
906019Shines@cs.fsu.edu  public:
9110037SARM gem5 Developers    /// Generic fault source enums used to index into
9210037SARM gem5 Developers    /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
9310037SARM gem5 Developers    /// on the current register width state and the translation table format in
9410037SARM gem5 Developers    /// use
9510037SARM gem5 Developers    enum FaultSource
967362Sgblack@eecs.umich.edu    {
9710037SARM gem5 Developers        AlignmentFault = 0,
9810037SARM gem5 Developers        InstructionCacheMaintenance,  // Short-desc. format only
9910037SARM gem5 Developers        SynchExtAbtOnTranslTableWalkLL,
10010037SARM gem5 Developers        SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
10110037SARM gem5 Developers        TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
10210037SARM gem5 Developers        AccessFlagLL = TranslationLL + 4,
10310037SARM gem5 Developers        DomainLL = AccessFlagLL + 4,
10410037SARM gem5 Developers        PermissionLL = DomainLL + 4,
10510037SARM gem5 Developers        DebugEvent = PermissionLL + 4,
10610037SARM gem5 Developers        SynchronousExternalAbort,
10710037SARM gem5 Developers        TLBConflictAbort,  // Requires LPAE
10810037SARM gem5 Developers        SynchPtyErrOnMemoryAccess,
10910037SARM gem5 Developers        AsynchronousExternalAbort,
11010037SARM gem5 Developers        AsynchPtyErrOnMemoryAccess,
11110037SARM gem5 Developers        AddressSizeLL,  // AArch64 only
1127611SGene.Wu@arm.com
11310037SARM gem5 Developers        // Not real faults. These are faults to allow the translation function
11410037SARM gem5 Developers        // to inform the memory access function not to proceed for a prefetch
11510037SARM gem5 Developers        // that misses in the TLB or that targets an uncacheable address
11610037SARM gem5 Developers        PrefetchTLBMiss = AddressSizeLL + 4,
11710037SARM gem5 Developers        PrefetchUncacheable,
11810037SARM gem5 Developers
11910037SARM gem5 Developers        NumFaultSources,
12010037SARM gem5 Developers        FaultSourceInvalid = 0xff
12110037SARM gem5 Developers    };
12210037SARM gem5 Developers
12310037SARM gem5 Developers    /// Encodings of the fault sources when the short-desc. translation table
12410037SARM gem5 Developers    /// format is in use (ARM ARM Issue C B3.13.3)
12510037SARM gem5 Developers    static uint8_t shortDescFaultSources[NumFaultSources];
12610037SARM gem5 Developers    /// Encodings of the fault sources when the long-desc. translation table
12710037SARM gem5 Developers    /// format is in use (ARM ARM Issue C B3.13.3)
12810037SARM gem5 Developers    static uint8_t longDescFaultSources[NumFaultSources];
12910037SARM gem5 Developers    /// Encodings of the fault sources in AArch64 state
13010037SARM gem5 Developers    static uint8_t aarch64FaultSources[NumFaultSources];
13110037SARM gem5 Developers
13210037SARM gem5 Developers    enum AnnotationIDs
13310037SARM gem5 Developers    {
13410037SARM gem5 Developers        S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
13510037SARM gem5 Developers        OVA,   // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
13610037SARM gem5 Developers        SAS,   // DataAbort: Syndrome Access Size
13710037SARM gem5 Developers        SSE,   // DataAbort: Syndrome Sign Extend
13810037SARM gem5 Developers        SRT,   // DataAbort: Syndrome Register Transfer
13910037SARM gem5 Developers
14010037SARM gem5 Developers        // AArch64 only
14110037SARM gem5 Developers        SF,    // DataAbort: width of the accessed register is SixtyFour
14210037SARM gem5 Developers        AR     // DataAbort: Acquire/Release semantics
14310037SARM gem5 Developers    };
14410037SARM gem5 Developers
14510037SARM gem5 Developers    enum TranMethod
14610037SARM gem5 Developers    {
14710037SARM gem5 Developers        LpaeTran,
14810037SARM gem5 Developers        VmsaTran,
14910037SARM gem5 Developers        UnknownTran
1507362Sgblack@eecs.umich.edu    };
1517362Sgblack@eecs.umich.edu
1526735Sgblack@eecs.umich.edu    struct FaultVals
1536735Sgblack@eecs.umich.edu    {
1546735Sgblack@eecs.umich.edu        const FaultName name;
15510037SARM gem5 Developers
1566735Sgblack@eecs.umich.edu        const FaultOffset offset;
15710037SARM gem5 Developers
15810037SARM gem5 Developers        // Offsets used for exceptions taken in AArch64 state
15910037SARM gem5 Developers        const uint16_t currELTOffset;
16010037SARM gem5 Developers        const uint16_t currELHOffset;
16110037SARM gem5 Developers        const uint16_t lowerEL64Offset;
16210037SARM gem5 Developers        const uint16_t lowerEL32Offset;
16310037SARM gem5 Developers
1646735Sgblack@eecs.umich.edu        const OperatingMode nextMode;
16510037SARM gem5 Developers
1666735Sgblack@eecs.umich.edu        const uint8_t armPcOffset;
1676735Sgblack@eecs.umich.edu        const uint8_t thumbPcOffset;
16810037SARM gem5 Developers        // The following two values are used in place of armPcOffset and
16910037SARM gem5 Developers        // thumbPcOffset when the exception return address is saved into ELR
17010037SARM gem5 Developers        // registers (exceptions taken in HYP mode or in AArch64 state)
17110037SARM gem5 Developers        const uint8_t armPcElrOffset;
17210037SARM gem5 Developers        const uint8_t thumbPcElrOffset;
17310037SARM gem5 Developers
17410037SARM gem5 Developers        const bool hypTrappable;
1756735Sgblack@eecs.umich.edu        const bool abortDisable;
1766735Sgblack@eecs.umich.edu        const bool fiqDisable;
17710037SARM gem5 Developers
17810037SARM gem5 Developers        // Exception class used to appropriately set the syndrome register
17910037SARM gem5 Developers        // (exceptions taken in HYP mode or in AArch64 state)
18010037SARM gem5 Developers        const ExceptionClass ec;
18110037SARM gem5 Developers
1826735Sgblack@eecs.umich.edu        FaultStat count;
18312517Srekai.gonzalezalberquilla@arm.com        FaultVals(const FaultName& name_, const FaultOffset& offset_,
18412517Srekai.gonzalezalberquilla@arm.com                const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
18512517Srekai.gonzalezalberquilla@arm.com                const uint16_t& lowerEL64Offset_,
18612517Srekai.gonzalezalberquilla@arm.com                const uint16_t& lowerEL32Offset_,
18712517Srekai.gonzalezalberquilla@arm.com                const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
18812517Srekai.gonzalezalberquilla@arm.com                const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
18912517Srekai.gonzalezalberquilla@arm.com                const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
19012517Srekai.gonzalezalberquilla@arm.com                const bool& abortDisable_, const bool& fiqDisable_,
19112517Srekai.gonzalezalberquilla@arm.com                const ExceptionClass& ec_)
19212517Srekai.gonzalezalberquilla@arm.com        : name(name_), offset(offset_), currELTOffset(currELTOffset_),
19312517Srekai.gonzalezalberquilla@arm.com          currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
19412517Srekai.gonzalezalberquilla@arm.com          lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
19512517Srekai.gonzalezalberquilla@arm.com          armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
19612517Srekai.gonzalezalberquilla@arm.com          armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
19712517Srekai.gonzalezalberquilla@arm.com          hypTrappable(hypTrappable_), abortDisable(abortDisable_),
19812517Srekai.gonzalezalberquilla@arm.com          fiqDisable(fiqDisable_), ec(ec_) {}
1996735Sgblack@eecs.umich.edu    };
2006735Sgblack@eecs.umich.edu
20110037SARM gem5 Developers    ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
20210537Sandreas.hansson@arm.com        machInst(_machInst), issRaw(_iss), from64(false), to64(false),
20312569Sgiacomo.travaglini@arm.com        fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
20414128Sgiacomo.travaglini@arm.com        faultUpdated(false), hypRouted(false), span(false) {}
20510037SARM gem5 Developers
20610037SARM gem5 Developers    // Returns the actual syndrome register to use based on the target
20710037SARM gem5 Developers    // exception level
20810037SARM gem5 Developers    MiscRegIndex getSyndromeReg64() const;
20910037SARM gem5 Developers    // Returns the actual fault address register to use based on the target
21010037SARM gem5 Developers    // exception level
21110037SARM gem5 Developers    MiscRegIndex getFaultAddrReg64() const;
21210037SARM gem5 Developers
21310417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
21412176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
21510417Sandreas.hansson@arm.com    void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
21610417Sandreas.hansson@arm.com                  StaticInst::nullStaticInstPtr);
21712569Sgiacomo.travaglini@arm.com    void update(ThreadContext *tc);
21813896Sgiacomo.travaglini@arm.com
21913896Sgiacomo.travaglini@arm.com    ArmStaticInst *instrAnnotate(const StaticInstPtr &inst);
22010037SARM gem5 Developers    virtual void annotate(AnnotationIDs id, uint64_t val) {}
2216735Sgblack@eecs.umich.edu    virtual FaultStat& countStat() = 0;
22210037SARM gem5 Developers    virtual FaultOffset offset(ThreadContext *tc) = 0;
22312511Schuan.zhu@arm.com    virtual FaultOffset offset64(ThreadContext *tc) = 0;
2246735Sgblack@eecs.umich.edu    virtual OperatingMode nextMode() = 0;
22510037SARM gem5 Developers    virtual bool routeToMonitor(ThreadContext *tc) const = 0;
22610037SARM gem5 Developers    virtual bool routeToHyp(ThreadContext *tc) const { return false; }
22710037SARM gem5 Developers    virtual uint8_t armPcOffset(bool isHyp) = 0;
22810037SARM gem5 Developers    virtual uint8_t thumbPcOffset(bool isHyp) = 0;
22910037SARM gem5 Developers    virtual uint8_t armPcElrOffset() = 0;
23010037SARM gem5 Developers    virtual uint8_t thumbPcElrOffset() = 0;
23110037SARM gem5 Developers    virtual bool abortDisable(ThreadContext *tc) = 0;
23210037SARM gem5 Developers    virtual bool fiqDisable(ThreadContext *tc) = 0;
23310037SARM gem5 Developers    virtual ExceptionClass ec(ThreadContext *tc) const = 0;
23410037SARM gem5 Developers    virtual uint32_t iss() const = 0;
23510037SARM gem5 Developers    virtual bool isStage2() const { return false; }
23612570Sgiacomo.travaglini@arm.com    virtual FSR getFsr(ThreadContext *tc) const { return 0; }
23710037SARM gem5 Developers    virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
23814091Sgabor.dozsa@arm.com    virtual bool getFaultVAddr(Addr &va) const { return false; }
23914091Sgabor.dozsa@arm.com
2406019Shines@cs.fsu.edu};
2416019Shines@cs.fsu.edu
2426735Sgblack@eecs.umich.edutemplate<typename T>
2437362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault
2446019Shines@cs.fsu.edu{
2456735Sgblack@eecs.umich.edu  protected:
2466735Sgblack@eecs.umich.edu    static FaultVals vals;
2476735Sgblack@eecs.umich.edu
2486019Shines@cs.fsu.edu  public:
24910037SARM gem5 Developers    ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
25010037SARM gem5 Developers        ArmFault(_machInst, _iss) {}
25112176Sandreas.sandberg@arm.com    FaultName name() const override { return vals.name; }
25212176Sandreas.sandberg@arm.com    FaultStat & countStat() override { return vals.count; }
25312176Sandreas.sandberg@arm.com    FaultOffset offset(ThreadContext *tc) override;
25410037SARM gem5 Developers
25512511Schuan.zhu@arm.com    FaultOffset offset64(ThreadContext *tc) override;
25610037SARM gem5 Developers
25712176Sandreas.sandberg@arm.com    OperatingMode nextMode() override { return vals.nextMode; }
25812176Sandreas.sandberg@arm.com    virtual bool routeToMonitor(ThreadContext *tc) const override {
25912176Sandreas.sandberg@arm.com        return false;
26012176Sandreas.sandberg@arm.com    }
26112176Sandreas.sandberg@arm.com    uint8_t armPcOffset(bool isHyp) override {
26212176Sandreas.sandberg@arm.com        return isHyp ? vals.armPcElrOffset
26312176Sandreas.sandberg@arm.com                     : vals.armPcOffset;
26412176Sandreas.sandberg@arm.com    }
26512176Sandreas.sandberg@arm.com    uint8_t thumbPcOffset(bool isHyp) override {
26612176Sandreas.sandberg@arm.com        return isHyp ? vals.thumbPcElrOffset
26712176Sandreas.sandberg@arm.com                     : vals.thumbPcOffset;
26812176Sandreas.sandberg@arm.com    }
26912176Sandreas.sandberg@arm.com    uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
27012176Sandreas.sandberg@arm.com    uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
27112176Sandreas.sandberg@arm.com    bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
27212176Sandreas.sandberg@arm.com    bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
27312176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
27412176Sandreas.sandberg@arm.com    uint32_t iss() const override { return issRaw; }
2756019Shines@cs.fsu.edu};
2766019Shines@cs.fsu.edu
2777400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset>
2787400SAli.Saidi@ARM.com{
27913396Sgiacomo.travaglini@arm.com  protected:
28013396Sgiacomo.travaglini@arm.com    Addr getVector(ThreadContext *tc) override;
28113396Sgiacomo.travaglini@arm.com
2827400SAli.Saidi@ARM.com  public:
28310417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
28412176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
2857400SAli.Saidi@ARM.com};
2867189Sgblack@eecs.umich.edu
2877362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
2887189Sgblack@eecs.umich.edu{
2897189Sgblack@eecs.umich.edu  protected:
2907189Sgblack@eecs.umich.edu    bool unknown;
2917640Sgblack@eecs.umich.edu    bool disabled;
29210037SARM gem5 Developers    ExceptionClass overrideEc;
29310205SAli.Saidi@ARM.com    const char *mnemonic;
2947189Sgblack@eecs.umich.edu
2957189Sgblack@eecs.umich.edu  public:
2967189Sgblack@eecs.umich.edu    UndefinedInstruction(ExtMachInst _machInst,
2977189Sgblack@eecs.umich.edu                         bool _unknown,
2987640Sgblack@eecs.umich.edu                         const char *_mnemonic = NULL,
2997640Sgblack@eecs.umich.edu                         bool _disabled = false) :
30010037SARM gem5 Developers        ArmFaultVals<UndefinedInstruction>(_machInst),
30110205SAli.Saidi@ARM.com        unknown(_unknown), disabled(_disabled),
30210205SAli.Saidi@ARM.com        overrideEc(EC_INVALID), mnemonic(_mnemonic)
30310037SARM gem5 Developers    {}
30410205SAli.Saidi@ARM.com    UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
30510205SAli.Saidi@ARM.com            ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
30610037SARM gem5 Developers        ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
30710205SAli.Saidi@ARM.com        unknown(false), disabled(true), overrideEc(_overrideEc),
30810205SAli.Saidi@ARM.com        mnemonic(_mnemonic)
3098782Sgblack@eecs.umich.edu    {}
3107189Sgblack@eecs.umich.edu
31110417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
31212176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
31312176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
31412176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
31512176Sandreas.sandberg@arm.com    uint32_t iss() const override;
3167189Sgblack@eecs.umich.edu};
3177189Sgblack@eecs.umich.edu
3187362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall>
3197197Sgblack@eecs.umich.edu{
3207197Sgblack@eecs.umich.edu  protected:
32110037SARM gem5 Developers    ExceptionClass overrideEc;
3227197Sgblack@eecs.umich.edu  public:
32310037SARM gem5 Developers    SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
32410037SARM gem5 Developers                   ExceptionClass _overrideEc = EC_INVALID) :
32510037SARM gem5 Developers        ArmFaultVals<SupervisorCall>(_machInst, _iss),
32610037SARM gem5 Developers        overrideEc(_overrideEc)
3278782Sgblack@eecs.umich.edu    {}
3287197Sgblack@eecs.umich.edu
32910417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
33012176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
33112176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
33212176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
33312176Sandreas.sandberg@arm.com    uint32_t iss() const override;
33410037SARM gem5 Developers};
33510037SARM gem5 Developers
33610037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
33710037SARM gem5 Developers{
33810037SARM gem5 Developers  public:
33910037SARM gem5 Developers    SecureMonitorCall(ExtMachInst _machInst) :
34010037SARM gem5 Developers        ArmFaultVals<SecureMonitorCall>(_machInst)
34110037SARM gem5 Developers    {}
34210037SARM gem5 Developers
34310417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
34412176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
34512176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
34612176Sandreas.sandberg@arm.com    uint32_t iss() const override;
34710037SARM gem5 Developers};
34810037SARM gem5 Developers
34910037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap>
35010037SARM gem5 Developers{
35110037SARM gem5 Developers  protected:
35210037SARM gem5 Developers    ExtMachInst machInst;
35310037SARM gem5 Developers    ExceptionClass overrideEc;
35410037SARM gem5 Developers
35510037SARM gem5 Developers  public:
35610037SARM gem5 Developers    SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
35710037SARM gem5 Developers                   ExceptionClass _overrideEc = EC_INVALID) :
35810037SARM gem5 Developers        ArmFaultVals<SupervisorTrap>(_machInst, _iss),
35910037SARM gem5 Developers        overrideEc(_overrideEc)
36010037SARM gem5 Developers    {}
36110037SARM gem5 Developers
36212509Schuan.zhu@arm.com    bool routeToHyp(ThreadContext *tc) const override;
36312509Schuan.zhu@arm.com    uint32_t iss() const override;
36412176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
36510037SARM gem5 Developers};
36610037SARM gem5 Developers
36710037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
36810037SARM gem5 Developers{
36910037SARM gem5 Developers protected:
37010037SARM gem5 Developers    ExtMachInst machInst;
37110037SARM gem5 Developers    ExceptionClass overrideEc;
37210037SARM gem5 Developers
37310037SARM gem5 Developers  public:
37410037SARM gem5 Developers    SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
37510037SARM gem5 Developers                      ExceptionClass _overrideEc = EC_INVALID) :
37610037SARM gem5 Developers        ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
37710037SARM gem5 Developers        overrideEc(_overrideEc)
37810037SARM gem5 Developers    {}
37910037SARM gem5 Developers
38012176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
38110037SARM gem5 Developers};
38210037SARM gem5 Developers
38310037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall>
38410037SARM gem5 Developers{
38510037SARM gem5 Developers  public:
38610037SARM gem5 Developers    HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
38711576SDylan.Johnson@ARM.com
38812176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
38910037SARM gem5 Developers};
39010037SARM gem5 Developers
39110037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap>
39210037SARM gem5 Developers{
39310037SARM gem5 Developers  protected:
39410037SARM gem5 Developers    ExtMachInst machInst;
39510037SARM gem5 Developers    ExceptionClass overrideEc;
39610037SARM gem5 Developers
39710037SARM gem5 Developers  public:
39810037SARM gem5 Developers    HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
39910037SARM gem5 Developers                   ExceptionClass _overrideEc = EC_INVALID) :
40010037SARM gem5 Developers      ArmFaultVals<HypervisorTrap>(_machInst, _iss),
40110037SARM gem5 Developers      overrideEc(_overrideEc)
40210037SARM gem5 Developers    {}
40310037SARM gem5 Developers
40412176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
4057197Sgblack@eecs.umich.edu};
4067362Sgblack@eecs.umich.edu
4077362Sgblack@eecs.umich.edutemplate <class T>
4087362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T>
4097362Sgblack@eecs.umich.edu{
4107362Sgblack@eecs.umich.edu  protected:
41110037SARM gem5 Developers    /**
41210037SARM gem5 Developers     * The virtual address the fault occured at. If 2 stages of
41310037SARM gem5 Developers     * translation are being used then this is the intermediate
41410037SARM gem5 Developers     * physical address that is the starting point for the second
41510037SARM gem5 Developers     * stage of translation.
41610037SARM gem5 Developers     */
4177362Sgblack@eecs.umich.edu    Addr faultAddr;
41810037SARM gem5 Developers    /**
41910037SARM gem5 Developers     * Original virtual address. If the fault was generated on the
42010037SARM gem5 Developers     * second stage of translation then this variable stores the
42110037SARM gem5 Developers     * virtual address used in the original stage 1 translation.
42210037SARM gem5 Developers     */
42310037SARM gem5 Developers    Addr OVAddr;
4247362Sgblack@eecs.umich.edu    bool write;
42510037SARM gem5 Developers    TlbEntry::DomainType domain;
42610037SARM gem5 Developers    uint8_t source;
42710037SARM gem5 Developers    uint8_t srcEncoded;
42810037SARM gem5 Developers    bool stage2;
42910037SARM gem5 Developers    bool s1ptw;
43010037SARM gem5 Developers    ArmFault::TranMethod tranMethod;
4317362Sgblack@eecs.umich.edu
4327362Sgblack@eecs.umich.edu  public:
43310537Sandreas.hansson@arm.com    AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
43410537Sandreas.hansson@arm.com               uint8_t _source, bool _stage2,
43510537Sandreas.hansson@arm.com               ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
43610537Sandreas.hansson@arm.com        faultAddr(_faultAddr), OVAddr(0), write(_write),
43710537Sandreas.hansson@arm.com        domain(_domain), source(_source), srcEncoded(0),
43810037SARM gem5 Developers        stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
4397362Sgblack@eecs.umich.edu    {}
4407362Sgblack@eecs.umich.edu
44114091Sgabor.dozsa@arm.com    bool getFaultVAddr(Addr &va) const override;
44214091Sgabor.dozsa@arm.com
44310417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
44412176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
44510037SARM gem5 Developers
44612570Sgiacomo.travaglini@arm.com    FSR getFsr(ThreadContext *tc) const override;
44712570Sgiacomo.travaglini@arm.com    uint8_t getFaultStatusCode(ThreadContext *tc) const;
44812176Sandreas.sandberg@arm.com    bool abortDisable(ThreadContext *tc) override;
44912176Sandreas.sandberg@arm.com    uint32_t iss() const override;
45012176Sandreas.sandberg@arm.com    bool isStage2() const override { return stage2; }
45112176Sandreas.sandberg@arm.com    void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
45212570Sgiacomo.travaglini@arm.com    void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
45310037SARM gem5 Developers    bool isMMUFault() const;
4547362Sgblack@eecs.umich.edu};
4557362Sgblack@eecs.umich.edu
4567362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort>
4577362Sgblack@eecs.umich.edu{
4587362Sgblack@eecs.umich.edu  public:
45910037SARM gem5 Developers    static const MiscRegIndex FsrIndex  = MISCREG_IFSR;
46010037SARM gem5 Developers    static const MiscRegIndex FarIndex  = MISCREG_IFAR;
46110037SARM gem5 Developers    static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
4627362Sgblack@eecs.umich.edu
46310037SARM gem5 Developers    PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
46410037SARM gem5 Developers                  ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
46510037SARM gem5 Developers        AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
46610037SARM gem5 Developers                _source, _stage2, _tranMethod)
4677362Sgblack@eecs.umich.edu    {}
46810037SARM gem5 Developers
46912176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
47010037SARM gem5 Developers    // @todo: external aborts should be routed if SCR.EA == 1
47112176Sandreas.sandberg@arm.com    bool routeToMonitor(ThreadContext *tc) const override;
47212176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
4737362Sgblack@eecs.umich.edu};
4747362Sgblack@eecs.umich.edu
4757362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort>
4767362Sgblack@eecs.umich.edu{
4777362Sgblack@eecs.umich.edu  public:
47810037SARM gem5 Developers    static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
47910037SARM gem5 Developers    static const MiscRegIndex FarIndex  = MISCREG_DFAR;
48010037SARM gem5 Developers    static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
48110037SARM gem5 Developers    bool    isv;
48210037SARM gem5 Developers    uint8_t sas;
48310037SARM gem5 Developers    uint8_t sse;
48410037SARM gem5 Developers    uint8_t srt;
4857362Sgblack@eecs.umich.edu
48610037SARM gem5 Developers    // AArch64 only
48710037SARM gem5 Developers    bool sf;
48810037SARM gem5 Developers    bool ar;
48910037SARM gem5 Developers
49010037SARM gem5 Developers    DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
49110037SARM gem5 Developers              bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
49210037SARM gem5 Developers        AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
49310037SARM gem5 Developers                              _tranMethod),
49410037SARM gem5 Developers        isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
4957362Sgblack@eecs.umich.edu    {}
49610037SARM gem5 Developers
49712176Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
49810037SARM gem5 Developers    // @todo: external aborts should be routed if SCR.EA == 1
49912176Sandreas.sandberg@arm.com    bool routeToMonitor(ThreadContext *tc) const override;
50012176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
50112176Sandreas.sandberg@arm.com    uint32_t iss() const override;
50212176Sandreas.sandberg@arm.com    void annotate(AnnotationIDs id, uint64_t val) override;
5037362Sgblack@eecs.umich.edu};
5047362Sgblack@eecs.umich.edu
50510037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort>
50610037SARM gem5 Developers{
50710037SARM gem5 Developers  public:
50810037SARM gem5 Developers    static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
50910037SARM gem5 Developers    static const MiscRegIndex FarIndex  = MISCREG_DFAR;
51010037SARM gem5 Developers    static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
51110037SARM gem5 Developers
51210037SARM gem5 Developers    VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
51310037SARM gem5 Developers                     uint8_t _source) :
51410037SARM gem5 Developers        AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
51510037SARM gem5 Developers    {}
51610037SARM gem5 Developers
51712176Sandreas.sandberg@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
51810037SARM gem5 Developers};
51910037SARM gem5 Developers
52010037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt>
52110037SARM gem5 Developers{
52210037SARM gem5 Developers  public:
52312176Sandreas.sandberg@arm.com    bool routeToMonitor(ThreadContext *tc) const override;
52412176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
52512176Sandreas.sandberg@arm.com    bool abortDisable(ThreadContext *tc) override;
52610037SARM gem5 Developers};
52710037SARM gem5 Developers
52810037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
52910037SARM gem5 Developers{
53010037SARM gem5 Developers  public:
53110037SARM gem5 Developers    VirtualInterrupt();
53210037SARM gem5 Developers};
53310037SARM gem5 Developers
53410037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt>
53510037SARM gem5 Developers{
53610037SARM gem5 Developers  public:
53712176Sandreas.sandberg@arm.com    bool routeToMonitor(ThreadContext *tc) const override;
53812176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
53912176Sandreas.sandberg@arm.com    bool abortDisable(ThreadContext *tc) override;
54012176Sandreas.sandberg@arm.com    bool fiqDisable(ThreadContext *tc) override;
54110037SARM gem5 Developers};
54210037SARM gem5 Developers
54310037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
54410037SARM gem5 Developers{
54510037SARM gem5 Developers  public:
54610037SARM gem5 Developers    VirtualFastInterrupt();
54710037SARM gem5 Developers};
54810037SARM gem5 Developers
54910037SARM gem5 Developers/// PC alignment fault (AArch64 only)
55010037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
55110037SARM gem5 Developers{
55210037SARM gem5 Developers  protected:
55310037SARM gem5 Developers    /// The unaligned value of the PC
55410037SARM gem5 Developers    Addr faultPC;
55510037SARM gem5 Developers  public:
55610037SARM gem5 Developers    PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
55710037SARM gem5 Developers    {}
55810417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
55912176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
56012568Sgiacomo.travaglini@arm.com    bool routeToHyp(ThreadContext *tc) const override;
56110037SARM gem5 Developers};
56210037SARM gem5 Developers
56310037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only)
56410037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
56510037SARM gem5 Developers{
56610037SARM gem5 Developers  public:
56710037SARM gem5 Developers    SPAlignmentFault();
56810037SARM gem5 Developers};
56910037SARM gem5 Developers
57010037SARM gem5 Developers/// System error (AArch64 only)
57110037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError>
57210037SARM gem5 Developers{
57310037SARM gem5 Developers  public:
57410037SARM gem5 Developers    SystemError();
57510417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
57612176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
57712176Sandreas.sandberg@arm.com    bool routeToMonitor(ThreadContext *tc) const override;
57812176Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
57910037SARM gem5 Developers};
5806019Shines@cs.fsu.edu
58112299Sandreas.sandberg@arm.com/// System error (AArch64 only)
58212299Sandreas.sandberg@arm.comclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
58312299Sandreas.sandberg@arm.com{
58412299Sandreas.sandberg@arm.com  public:
58512299Sandreas.sandberg@arm.com    SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
58612299Sandreas.sandberg@arm.com
58712299Sandreas.sandberg@arm.com    bool routeToHyp(ThreadContext *tc) const override;
58812732Sandreas.sandberg@arm.com    ExceptionClass ec(ThreadContext *tc) const override;
58912299Sandreas.sandberg@arm.com};
59012299Sandreas.sandberg@arm.com
5917652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions
5928518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev>
5938518Sgeoffrey.blake@arm.com{
5948518Sgeoffrey.blake@arm.com  public:
5958518Sgeoffrey.blake@arm.com    ArmSev () {}
59610417Sandreas.hansson@arm.com    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
59712176Sandreas.sandberg@arm.com                StaticInst::nullStaticInstPtr) override;
5988518Sgeoffrey.blake@arm.com};
5998518Sgeoffrey.blake@arm.com
60010037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only)
60110037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
60210037SARM gem5 Developers{
60310037SARM gem5 Developers  public:
60410037SARM gem5 Developers    IllegalInstSetStateFault();
60510037SARM gem5 Developers};
60610037SARM gem5 Developers
60711929SMatteo.Andreozzi@arm.com/*
60812032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings
60912032Sandreas.sandberg@arm.com * in some clang versions
61011929SMatteo.Andreozzi@arm.com */
61111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals;
61211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals;
61311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals;
61411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals;
61511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals;
61611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals;
61711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals;
61811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals;
61911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals;
62011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
62111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals;
62211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals;
62311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals;
62413456Snikos.nikoleris@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals;
62511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals;
62611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals;
62711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
62811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
62911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
63012299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals;
63111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
63211929SMatteo.Andreozzi@arm.com
63314091Sgabor.dozsa@arm.com/**
63414091Sgabor.dozsa@arm.com * Returns true if the fault passed as a first argument was triggered
63514091Sgabor.dozsa@arm.com * by a memory access, false otherwise.
63614091Sgabor.dozsa@arm.com * If true it is storing the faulting address in the va argument
63714091Sgabor.dozsa@arm.com *
63814091Sgabor.dozsa@arm.com * @param fault generated fault
63914091Sgabor.dozsa@arm.com * @param va function will modify this passed-by-reference parameter
64014091Sgabor.dozsa@arm.com *           with the correct faulting virtual address
64114091Sgabor.dozsa@arm.com * @return true if va contains a valid value, false otherwise
64214091Sgabor.dozsa@arm.com */
64314091Sgabor.dozsa@arm.combool getFaultVAddr(Fault fault, Addr &va);
64414091Sgabor.dozsa@arm.com
64511929SMatteo.Andreozzi@arm.com
6467811Ssteve.reinhardt@amd.com} // namespace ArmISA
6476019Shines@cs.fsu.edu
6486019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__
649