1/*
2 * Copyright (c) 2011,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 *          Giacomo Travaglini
39 */
40
41/**
42 * @file: This file contains the data structure used to rappresent
43 *        Tarmac entities/informations. These data structures will
44 *        be used and extended by either the Tarmac Parser and
45 *        the Tarmac Tracer.
46 *        Instruction execution is matched by Records, so that for
47 *        every instruction executed there is a corresponding record.
48 *        A trace is made of Records (Generated or Parsed) and a record
49 *        is made of Entries.
50 */
51
52#ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
53#define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
54
55#include "arch/arm/registers.hh"
56#include "base/trace.hh"
57#include "base/types.hh"
58#include "cpu/static_inst.hh"
59#include "sim/insttracer.hh"
60
61class ThreadContext;
62
63namespace Trace {
64
65class TarmacBaseRecord : public InstRecord
66{
67  public:
68    /** TARMAC trace record type. */
69    enum TarmacRecordType {
70        TARMAC_INST,
71        TARMAC_REG,
72        TARMAC_MEM,
73        TARMAC_UNSUPPORTED,
74    };
75
76    /** ARM instruction set state. */
77    enum ISetState { ISET_ARM, ISET_THUMB, ISET_A64,
78                     ISET_UNSUPPORTED };
79
80    /** ARM register type. */
81    enum RegType { REG_R, REG_X, REG_S, REG_D, REG_Q, REG_MISC };
82
83    /** TARMAC instruction trace record. */
84    struct InstEntry
85    {
86        InstEntry() = default;
87        InstEntry(ThreadContext* thread,
88                  ArmISA::PCState pc,
89                  const StaticInstPtr staticInst,
90                  bool predicate);
91
92        bool taken;
93        Addr addr;
94        ArmISA::MachInst opcode;
95        std::string disassemble;
96        ISetState isetstate;
97        ArmISA::OperatingMode mode;
98    };
99
100    /** TARMAC register trace record. */
101    struct RegEntry
102    {
103        RegEntry() = default;
104        RegEntry(ArmISA::PCState pc);
105
106        RegType type;
107        RegIndex index;
108        ISetState isetstate;
109        uint64_t valueHi;
110        uint64_t valueLo;
111    };
112
113    /** TARMAC memory access trace record (stores only). */
114    struct MemEntry
115    {
116        MemEntry() = default;
117        MemEntry(uint8_t _size, Addr _addr, uint64_t _data);
118
119        uint8_t size;
120        Addr addr;
121        uint64_t data;
122    };
123
124  public:
125    TarmacBaseRecord(Tick _when, ThreadContext *_thread,
126                     const StaticInstPtr _staticInst, ArmISA::PCState _pc,
127                     const StaticInstPtr _macroStaticInst = NULL);
128
129    virtual void dump() = 0;
130
131    /**
132     * Returns the Instruction Set State according to the current
133     * PCState.
134     *
135     * @param pc program counter (PCState) variable
136     * @return Instruction Set State for the given PCState
137     */
138    static ISetState pcToISetState(ArmISA::PCState pc);
139};
140
141
142} // namespace Trace
143
144#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
145