1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Alec Roelke
31 *          Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <string>
38
39#include "arch/riscv/isa.hh"
40#include "arch/riscv/registers.hh"
41#include "cpu/thread_context.hh"
42#include "sim/faults.hh"
43
44namespace RiscvISA
45{
46
47enum FloatException : uint64_t {
48    FloatInexact = 0x1,
49    FloatUnderflow = 0x2,
50    FloatOverflow = 0x4,
51    FloatDivZero = 0x8,
52    FloatInvalid = 0x10
53};
54
55/*
56 * In RISC-V, exception and interrupt codes share some values. They can be
57 * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
58 * but not exceptions. The full fault cause can be computed by placing the
59 * exception (or interrupt) code in the least significant bits of the CAUSE
60 * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
61 * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
62 * privileged specification v 1.10. Codes are enumerated in Table 3.6.
63 */
64enum ExceptionCode : uint64_t {
65    INST_ADDR_MISALIGNED = 0,
66    INST_ACCESS = 1,
67    INST_ILLEGAL = 2,
68    BREAKPOINT = 3,
69    LOAD_ADDR_MISALIGNED = 4,
70    LOAD_ACCESS = 5,
71    STORE_ADDR_MISALIGNED = 6,
72    AMO_ADDR_MISALIGNED = 6,
73    STORE_ACCESS = 7,
74    AMO_ACCESS = 7,
75    ECALL_USER = 8,
76    ECALL_SUPER = 9,
77    ECALL_MACHINE = 11,
78    INST_PAGE = 12,
79    LOAD_PAGE = 13,
80    STORE_PAGE = 15,
81    AMO_PAGE = 15,
82
83    INT_SOFTWARE_USER = 0,
84    INT_SOFTWARE_SUPER = 1,
85    INT_SOFTWARE_MACHINE = 3,
86    INT_TIMER_USER = 4,
87    INT_TIMER_SUPER = 5,
88    INT_TIMER_MACHINE = 7,
89    INT_EXT_USER = 8,
90    INT_EXT_SUPER = 9,
91    INT_EXT_MACHINE = 11,
92    NumInterruptTypes
93};
94
95class RiscvFault : public FaultBase
96{
97  protected:
98    const FaultName _name;
99    const bool _interrupt;
100    ExceptionCode _code;
101
102    RiscvFault(FaultName n, bool i, ExceptionCode c)
103        : _name(n), _interrupt(i), _code(c)
104    {}
105
106    FaultName name() const override { return _name; }
107    bool isInterrupt() const { return _interrupt; }
108    ExceptionCode exception() const { return _code; }
109    virtual RegVal trap_value() const { return 0; }
110
111    virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
112    void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
113};
114
115class Reset : public FaultBase
116{
117  private:
118    const FaultName _name;
119
120  public:
121    Reset() : _name("reset") {}
122    FaultName name() const override { return _name; }
123
124    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
125        StaticInst::nullStaticInstPtr) override;
126};
127
128class InterruptFault : public RiscvFault
129{
130  public:
131    InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {}
132    InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {}
133};
134
135class InstFault : public RiscvFault
136{
137  protected:
138    const ExtMachInst _inst;
139
140  public:
141    InstFault(FaultName n, const ExtMachInst inst)
142        : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
143    {}
144
145    RegVal trap_value() const override { return _inst; }
146};
147
148class UnknownInstFault : public InstFault
149{
150  public:
151    UnknownInstFault(const ExtMachInst inst)
152        : InstFault("Unknown instruction", inst)
153    {}
154
155    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
156};
157
158class IllegalInstFault : public InstFault
159{
160  private:
161    const std::string reason;
162
163  public:
164    IllegalInstFault(std::string r, const ExtMachInst inst)
165        : InstFault("Illegal instruction", inst)
166    {}
167
168    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
169};
170
171class UnimplementedFault : public InstFault
172{
173  private:
174    const std::string instName;
175
176  public:
177    UnimplementedFault(std::string name, const ExtMachInst inst)
178        : InstFault("Unimplemented instruction", inst),
179          instName(name)
180    {}
181
182    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
183};
184
185class IllegalFrmFault: public InstFault
186{
187  private:
188    const uint8_t frm;
189
190  public:
191    IllegalFrmFault(uint8_t r, const ExtMachInst inst)
192        : InstFault("Illegal floating-point rounding mode", inst),
193          frm(r)
194    {}
195
196    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
197};
198
199class AddressFault : public RiscvFault
200{
201  private:
202    const Addr _addr;
203
204  public:
205    AddressFault(const Addr addr, ExceptionCode code)
206        : RiscvFault("Address", false, code), _addr(addr)
207    {}
208
209    RegVal trap_value() const override { return _addr; }
210};
211
212class BreakpointFault : public RiscvFault
213{
214  private:
215    const PCState pcState;
216
217  public:
218    BreakpointFault(const PCState &pc)
219        : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
220    {}
221
222    RegVal trap_value() const override { return pcState.pc(); }
223    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
224};
225
226class SyscallFault : public RiscvFault
227{
228  public:
229    SyscallFault(PrivilegeMode prv)
230        : RiscvFault("System call", false, ECALL_USER)
231    {
232        switch (prv) {
233          case PRV_U:
234            _code = ECALL_USER;
235            break;
236          case PRV_S:
237            _code = ECALL_SUPER;
238            break;
239          case PRV_M:
240            _code = ECALL_MACHINE;
241            break;
242          default:
243            panic("Unknown privilege mode %d.", prv);
244            break;
245        }
246    }
247
248    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
249};
250
251} // namespace RiscvISA
252
253#endif // __ARCH_RISCV_FAULTS_HH__
254