112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2011,2017-2018 ARM Limited 312641Sgiacomo.travaglini@arm.com * All rights reserved 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612641Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712641Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812641Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912641Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012641Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112641Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212641Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312641Sgiacomo.travaglini@arm.com * 1412641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412641Sgiacomo.travaglini@arm.com * 2512641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612641Sgiacomo.travaglini@arm.com * 3712641Sgiacomo.travaglini@arm.com * Authors: Giacomo Gabrielli 3812641Sgiacomo.travaglini@arm.com * Giacomo Travaglini 3912641Sgiacomo.travaglini@arm.com */ 4012641Sgiacomo.travaglini@arm.com 4112641Sgiacomo.travaglini@arm.com/** 4212641Sgiacomo.travaglini@arm.com * @file: This file contains the data structure used to rappresent 4312641Sgiacomo.travaglini@arm.com * Tarmac entities/informations. These data structures will 4412641Sgiacomo.travaglini@arm.com * be used and extended by either the Tarmac Parser and 4512641Sgiacomo.travaglini@arm.com * the Tarmac Tracer. 4612641Sgiacomo.travaglini@arm.com * Instruction execution is matched by Records, so that for 4712641Sgiacomo.travaglini@arm.com * every instruction executed there is a corresponding record. 4812641Sgiacomo.travaglini@arm.com * A trace is made of Records (Generated or Parsed) and a record 4912641Sgiacomo.travaglini@arm.com * is made of Entries. 5012641Sgiacomo.travaglini@arm.com */ 5112641Sgiacomo.travaglini@arm.com 5212641Sgiacomo.travaglini@arm.com#ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 5312641Sgiacomo.travaglini@arm.com#define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 5412641Sgiacomo.travaglini@arm.com 5512641Sgiacomo.travaglini@arm.com#include "arch/arm/registers.hh" 5612641Sgiacomo.travaglini@arm.com#include "base/trace.hh" 5712641Sgiacomo.travaglini@arm.com#include "base/types.hh" 5812641Sgiacomo.travaglini@arm.com#include "cpu/static_inst.hh" 5912641Sgiacomo.travaglini@arm.com#include "sim/insttracer.hh" 6012641Sgiacomo.travaglini@arm.com 6112641Sgiacomo.travaglini@arm.comclass ThreadContext; 6212641Sgiacomo.travaglini@arm.com 6312641Sgiacomo.travaglini@arm.comnamespace Trace { 6412641Sgiacomo.travaglini@arm.com 6512641Sgiacomo.travaglini@arm.comclass TarmacBaseRecord : public InstRecord 6612641Sgiacomo.travaglini@arm.com{ 6712641Sgiacomo.travaglini@arm.com public: 6812641Sgiacomo.travaglini@arm.com /** TARMAC trace record type. */ 6912641Sgiacomo.travaglini@arm.com enum TarmacRecordType { 7012641Sgiacomo.travaglini@arm.com TARMAC_INST, 7112641Sgiacomo.travaglini@arm.com TARMAC_REG, 7212641Sgiacomo.travaglini@arm.com TARMAC_MEM, 7312641Sgiacomo.travaglini@arm.com TARMAC_UNSUPPORTED, 7412641Sgiacomo.travaglini@arm.com }; 7512641Sgiacomo.travaglini@arm.com 7612641Sgiacomo.travaglini@arm.com /** ARM instruction set state. */ 7712641Sgiacomo.travaglini@arm.com enum ISetState { ISET_ARM, ISET_THUMB, ISET_A64, 7812641Sgiacomo.travaglini@arm.com ISET_UNSUPPORTED }; 7912641Sgiacomo.travaglini@arm.com 8012641Sgiacomo.travaglini@arm.com /** ARM register type. */ 8112641Sgiacomo.travaglini@arm.com enum RegType { REG_R, REG_X, REG_S, REG_D, REG_Q, REG_MISC }; 8212641Sgiacomo.travaglini@arm.com 8312641Sgiacomo.travaglini@arm.com /** TARMAC instruction trace record. */ 8412641Sgiacomo.travaglini@arm.com struct InstEntry 8512641Sgiacomo.travaglini@arm.com { 8612641Sgiacomo.travaglini@arm.com InstEntry() = default; 8712641Sgiacomo.travaglini@arm.com InstEntry(ThreadContext* thread, 8813915Sgabeblack@google.com ArmISA::PCState pc, 8912641Sgiacomo.travaglini@arm.com const StaticInstPtr staticInst, 9012641Sgiacomo.travaglini@arm.com bool predicate); 9112641Sgiacomo.travaglini@arm.com 9212641Sgiacomo.travaglini@arm.com bool taken; 9312641Sgiacomo.travaglini@arm.com Addr addr; 9412641Sgiacomo.travaglini@arm.com ArmISA::MachInst opcode; 9512641Sgiacomo.travaglini@arm.com std::string disassemble; 9612641Sgiacomo.travaglini@arm.com ISetState isetstate; 9712641Sgiacomo.travaglini@arm.com ArmISA::OperatingMode mode; 9812641Sgiacomo.travaglini@arm.com }; 9912641Sgiacomo.travaglini@arm.com 10012641Sgiacomo.travaglini@arm.com /** TARMAC register trace record. */ 10112641Sgiacomo.travaglini@arm.com struct RegEntry 10212641Sgiacomo.travaglini@arm.com { 10312641Sgiacomo.travaglini@arm.com RegEntry() = default; 10413915Sgabeblack@google.com RegEntry(ArmISA::PCState pc); 10512641Sgiacomo.travaglini@arm.com 10612641Sgiacomo.travaglini@arm.com RegType type; 10712641Sgiacomo.travaglini@arm.com RegIndex index; 10812641Sgiacomo.travaglini@arm.com ISetState isetstate; 10912641Sgiacomo.travaglini@arm.com uint64_t valueHi; 11012641Sgiacomo.travaglini@arm.com uint64_t valueLo; 11112641Sgiacomo.travaglini@arm.com }; 11212641Sgiacomo.travaglini@arm.com 11312641Sgiacomo.travaglini@arm.com /** TARMAC memory access trace record (stores only). */ 11412641Sgiacomo.travaglini@arm.com struct MemEntry 11512641Sgiacomo.travaglini@arm.com { 11612641Sgiacomo.travaglini@arm.com MemEntry() = default; 11712641Sgiacomo.travaglini@arm.com MemEntry(uint8_t _size, Addr _addr, uint64_t _data); 11812641Sgiacomo.travaglini@arm.com 11912641Sgiacomo.travaglini@arm.com uint8_t size; 12012641Sgiacomo.travaglini@arm.com Addr addr; 12112641Sgiacomo.travaglini@arm.com uint64_t data; 12212641Sgiacomo.travaglini@arm.com }; 12312641Sgiacomo.travaglini@arm.com 12412641Sgiacomo.travaglini@arm.com public: 12512641Sgiacomo.travaglini@arm.com TarmacBaseRecord(Tick _when, ThreadContext *_thread, 12613915Sgabeblack@google.com const StaticInstPtr _staticInst, ArmISA::PCState _pc, 12712641Sgiacomo.travaglini@arm.com const StaticInstPtr _macroStaticInst = NULL); 12812641Sgiacomo.travaglini@arm.com 12912641Sgiacomo.travaglini@arm.com virtual void dump() = 0; 13012641Sgiacomo.travaglini@arm.com 13112641Sgiacomo.travaglini@arm.com /** 13212641Sgiacomo.travaglini@arm.com * Returns the Instruction Set State according to the current 13312641Sgiacomo.travaglini@arm.com * PCState. 13412641Sgiacomo.travaglini@arm.com * 13512641Sgiacomo.travaglini@arm.com * @param pc program counter (PCState) variable 13612641Sgiacomo.travaglini@arm.com * @return Instruction Set State for the given PCState 13712641Sgiacomo.travaglini@arm.com */ 13813915Sgabeblack@google.com static ISetState pcToISetState(ArmISA::PCState pc); 13912641Sgiacomo.travaglini@arm.com}; 14012641Sgiacomo.travaglini@arm.com 14112641Sgiacomo.travaglini@arm.com 14212641Sgiacomo.travaglini@arm.com} // namespace Trace 14312641Sgiacomo.travaglini@arm.com 14412641Sgiacomo.travaglini@arm.com#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 145