Searched refs:ReturnValueReg (Results 1 - 12 of 12) sorted by relevance
| /gem5/src/arch/arm/ |
| H A D | registers.hh | 112 const int ReturnValueReg = 0; member in namespace:ArmISA
128 const int SyscallNumReg = ReturnValueReg;
129 const int SyscallPseudoReturnReg = ReturnValueReg;
130 const int SyscallSuccessReg = ReturnValueReg;
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| H A D | process.cc | 550 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
567 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
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| /gem5/src/arch/sparc/ |
| H A D | registers.hh | 68 const int ReturnValueReg = 8; // Post return, 24 is pre-return. member in namespace:SparcISA
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| H A D | process.cc | 547 tc->setIntReg(ReturnValueReg, val);
555 tc->setIntReg(ReturnValueReg, val);
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| /gem5/src/arch/power/ |
| H A D | registers.hh | 84 const int ReturnValueReg = 3; member in namespace:PowerISA
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| H A D | process.cc | 300 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
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| /gem5/src/arch/x86/ |
| H A D | registers.hh | 92 const int ReturnValueReg = INTREG_RAX; member in namespace:X86ISA
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| /gem5/src/arch/alpha/ |
| H A D | registers.hh | 81 const RegIndex ReturnValueReg = 0; member in namespace:AlphaISA
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| H A D | process.cc | 247 tc->setIntReg(ReturnValueReg, sysret.returnValue());
251 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
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| /gem5/src/arch/mips/ |
| H A D | registers.hh | 114 const int ReturnValueReg = 2; member in namespace:MipsISA
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| H A D | process.cc | 221 tc->setIntReg(ReturnValueReg, sysret.returnValue());
225 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
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| /gem5/src/arch/riscv/ |
| H A D | registers.hh | 106 const int ReturnValueReg = 10; member in namespace:RiscvISA
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