1/*
2 * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/ccregs.hh"
47#include "arch/arm/generated/max_inst_regs.hh"
48#include "arch/arm/intregs.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "arch/generic/vec_pred_reg.hh"
52#include "arch/generic/vec_reg.hh"
53
54namespace ArmISA {
55
56
57// For a predicated instruction, we need all the
58// destination registers to also be sources
59const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
60    ArmISAInst::MaxInstSrcRegs;
61using ArmISAInst::MaxInstDestRegs;
62using ArmISAInst::MaxMiscDestRegs;
63
64// Number of VecElem per Vector Register considering only pre-SVE
65// Advanced SIMD registers.
66constexpr unsigned NumVecElemPerNeonVecReg = 4;
67// Number of VecElem per Vector Register, computed based on the vector length
68constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
69
70using VecElem = uint32_t;
71using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
72using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
73using VecRegContainer = VecReg::Container;
74
75using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
76                                 VecPredRegHasPackedRepr, false>;
77using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
78                                      VecPredRegHasPackedRepr, true>;
79using VecPredRegContainer = VecPredReg::Container;
80
81// Constants Related to the number of registers
82const int NumIntArchRegs = NUM_ARCH_INTREGS;
83// The number of single precision floating point registers
84const int NumFloatV7ArchRegs  = 64;
85const int NumFloatV8ArchRegs  = 128;
86const int NumFloatSpecialRegs = 32;
87const int NumVecV7ArchRegs  = 64;
88const int NumVecV8ArchRegs  = 32;
89const int NumVecSpecialRegs = 8;
90
91const int NumVecIntrlvRegs = 4;
92const int NumIntRegs = NUM_INTREGS;
93const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
94const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
95const int VECREG_UREG0 = 32;
96const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
97const int PREDREG_FFR = 16;
98const int PREDREG_UREG0 = 17;
99const int NumCCRegs = NUM_CCREGS;
100const int NumMiscRegs = NUM_MISCREGS;
101const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
102const int INTRLVREG1 = INTRLVREG0 + 1;
103const int INTRLVREG2 = INTRLVREG0 + 2;
104const int INTRLVREG3 = INTRLVREG0 + 3;
105
106#define ISA_HAS_CC_REGS
107
108const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
109    NumVecPredRegs + NumMiscRegs;
110
111// semantically meaningful register indices
112const int ReturnValueReg = 0;
113const int ReturnValueReg1 = 1;
114const int ReturnValueReg2 = 2;
115const int NumArgumentRegs = 4;
116const int NumArgumentRegs64 = 8;
117const int ArgumentReg0 = 0;
118const int ArgumentReg1 = 1;
119const int ArgumentReg2 = 2;
120const int ArgumentReg3 = 3;
121const int FramePointerReg = 11;
122const int StackPointerReg = INTREG_SP;
123const int ReturnAddressReg = INTREG_LR;
124const int PCReg = INTREG_PC;
125
126const int ZeroReg = INTREG_ZERO;
127
128const int SyscallNumReg = ReturnValueReg;
129const int SyscallPseudoReturnReg = ReturnValueReg;
130const int SyscallSuccessReg = ReturnValueReg;
131
132} // namespace ArmISA
133
134#endif
135