1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
34#include "arch/generic/vec_pred_reg.hh"
35#include "arch/generic/vec_reg.hh"
36#include "arch/power/generated/max_inst_regs.hh"
37#include "arch/power/miscregs.hh"
38#include "base/types.hh"
39
40namespace PowerISA {
41
42using PowerISAInst::MaxInstSrcRegs;
43using PowerISAInst::MaxInstDestRegs;
44
45// Power writes a misc register outside of the isa parser, so it can't
46// be detected by it. Manually add it here.
47const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
48
49// Not applicable to Power
50using VecElem = ::DummyVecElem;
51using VecReg = ::DummyVecReg;
52using ConstVecReg = ::DummyConstVecReg;
53using VecRegContainer = ::DummyVecRegContainer;
54constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
55constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
56
57// Not applicable to Power
58using VecPredReg = ::DummyVecPredReg;
59using ConstVecPredReg = ::DummyConstVecPredReg;
60using VecPredRegContainer = ::DummyVecPredRegContainer;
61constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
62constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
63
64// Constants Related to the number of registers
65const int NumIntArchRegs = 32;
66
67// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
68// and zero register, which doesn't actually exist but needs a number
69const int NumIntSpecialRegs = 9;
70const int NumFloatArchRegs = 32;
71const int NumFloatSpecialRegs = 0;
72const int NumInternalProcRegs = 0;
73
74const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
75const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
76const int NumVecRegs = 1;  // Not applicable to Power
77                           // (1 to prevent warnings)
78const int NumVecPredRegs = 1;  // Not applicable to Power
79                               // (1 to prevent warnings)
80const int NumCCRegs = 0;
81const int NumMiscRegs = NUM_MISCREGS;
82
83// Semantically meaningful register indices
84const int ReturnValueReg = 3;
85const int ArgumentReg0 = 3;
86const int ArgumentReg1 = 4;
87const int ArgumentReg2 = 5;
88const int ArgumentReg3 = 6;
89const int ArgumentReg4 = 7;
90const int FramePointerReg = 31;
91const int StackPointerReg = 1;
92
93// There isn't one in Power, but we need to define one somewhere
94const int ZeroReg = NumIntRegs - 1;
95
96const int SyscallNumReg = 0;
97const int SyscallPseudoReturnReg = 3;
98const int SyscallSuccessReg = 3;
99
100enum MiscIntRegNums {
101    INTREG_CR = NumIntArchRegs,
102    INTREG_XER,
103    INTREG_LR,
104    INTREG_CTR,
105    INTREG_FPSCR,
106    INTREG_RSV,
107    INTREG_RSV_LEN,
108    INTREG_RSV_ADDR
109};
110
111} // namespace PowerISA
112
113#endif // __ARCH_POWER_REGISTERS_HH__
114