Searched refs:NumCCRegs (Results 1 - 20 of 20) sorted by relevance

/gem5/src/arch/x86/
H A Dregisters.hh61 const int NumCCRegs = NUM_CCREGS; member in namespace:X86ISA
77 Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
H A Dutility.cc244 for (int i = 0; i < NumCCRegs; ++i)
/gem5/src/arch/power/
H A Dutility.cc53 assert(NumCCRegs == 0);
H A Dregisters.hh80 const int NumCCRegs = 0; member in namespace:PowerISA
/gem5/src/arch/sparc/
H A Dregisters.hh81 const int NumCCRegs = 0; member in namespace:SparcISA
H A Dutility.cc239 assert(NumCCRegs == 0);
/gem5/src/cpu/
H A Dthread_context.cc110 for (int i = 0; i < TheISA::NumCCRegs; ++i) {
195 RegVal ccRegs[NumCCRegs];
196 for (int i = 0; i < NumCCRegs; ++i)
198 SERIALIZE_ARRAY(ccRegs, NumCCRegs);
236 RegVal ccRegs[NumCCRegs];
237 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
238 for (int i = 0; i < NumCCRegs; ++i)
H A Dsimple_thread.hh111 RegVal ccRegs[TheISA::NumCCRegs];
447 assert(flatIndex < TheISA::NumCCRegs);
516 assert(flatIndex < TheISA::NumCCRegs);
/gem5/src/arch/alpha/
H A Dregisters.hh99 const int NumCCRegs = 0; member in namespace:AlphaISA
H A Dutility.cc76 assert(NumCCRegs == 0);
/gem5/src/cpu/minor/
H A Dscoreboard.cc66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
71 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
76 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
81 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
H A Dscoreboard.hh65 * CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1]
67 * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
96 numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
/gem5/src/arch/arm/
H A Dregisters.hh99 const int NumCCRegs = NUM_CCREGS; member in namespace:ArmISA
H A Dutility.cc175 for (int i = 0; i < NumCCRegs; i++)
/gem5/src/arch/mips/
H A Dregisters.hh63 const int NumCCRegs = 0; member in namespace:MipsISA
H A Dutility.cc253 assert(NumCCRegs == 0);
/gem5/src/cpu/o3/
H A Drename_map.cc132 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
H A Dregfile.cc81 if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
H A Dcpu.cc216 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
290 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
801 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
/gem5/src/arch/riscv/
H A Dregisters.hh97 const int NumCCRegs = 0; member in namespace:RiscvISA

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