/gem5/src/mem/ |
H A D | se_translating_port_proxy.cc | 122 SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const argument 137 PortProxy::memsetBlobPhys(paddr, 0, val, gen.size());
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/gem5/src/arch/arm/ |
H A D | isa.cc | 437 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 439 if (val & reg.res0()) { 441 miscRegName[misc_reg], val & reg.res0()); 443 if ((val & reg.res1()) != reg.res1()) { 445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 447 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 507 val &= cpacrMask; 509 miscRegName[misc_reg], val); 510 return val; 688 RegVal val = readMiscRegNoEffect(misc_reg); variable [all...] |
H A D | process.cc | 423 auxv[i].val = platform_base; 426 auxv[i].val = aux_data_base; 429 auxv[i].val = aux_random_base; 509 uint64_t val; 510 val = tc->readIntReg(ArgumentReg0 + i++); 511 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 512 return val; 523 ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 526 tc->setIntReg(ArgumentReg0 + i, val); 530 ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument [all...] |
H A D | faults.cc | 1188 AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) argument 1193 s1ptw = val; 1196 OVAddr = val; 1209 uint32_t val; local 1211 val = srcEncoded & 0x3F; 1212 val |= write << 6; 1213 val |= s1ptw << 7; 1214 return (val); 1368 uint32_t val; local 1371 val 1390 annotate(AnnotationIDs id, uint64_t val) argument [all...] |
/gem5/src/gpu-compute/ |
H A D | tlb_coalescer.hh | 153 Tick tickToCycles(Tick val) const { return val / clock;}
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H A D | wavefront.hh | 141 setLaneAddr(int lane, int addr, CType val) argument 143 *((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val; 316 writeCallArgMem(int lane, int addr, CType val) argument 318 callArgMem->setLaneAddr<CType>(lane, addr, val);
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/gem5/src/python/m5/util/ |
H A D | jobfile.py | 44 for key,val in obj.__dict__.items(): 49 self.__dict__[key] = val 52 if not isinstance(val, dict): 53 if self.__dict__[key] == val: 58 (key, self.__dict__[key], val)) 61 for k,v in val.items(): 86 val = self[key] 87 if isinstance(val, dict): 89 val = pprint.pformat(val) [all...] |
/gem5/ext/mcpat/cacti/ |
H A D | Ucache.h | 53 void update_min_values(const min_values_t * val);
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/gem5/src/dev/net/ |
H A D | sinicreg.hh | 44 static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \ 45 { return (reg & ~NAME) | ((val << OFFSET) & NAME); } 54 static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \ 55 { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
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/gem5/src/dev/arm/ |
H A D | timer_sp804.hh | 110 /** Restart the counter ticking at val 111 * @param val the value to start at (pre-16 bit masking if en) */ 112 void restartCounter(uint32_t val);
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H A D | timer_sp804.cc | 176 Sp804::Timer::restartCounter(uint32_t val) argument 178 DPRINTF(Timer, "Resetting counter with value %#x\n", val); 184 time *= val; 186 time *= bits(val,15,0);
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/gem5/src/systemc/ext/core/ |
H A D | sc_time.hh | 92 uint64_t val; member in class:sc_core::sc_time
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/gem5/src/systemc/core/ |
H A D | sc_module.cc | 288 sc_module::reset_signal_is(const sc_in<bool> &port, bool val) argument 290 ::sc_gem5::newReset(&port, ::sc_gem5::Process::newest(), true, val); 294 sc_module::reset_signal_is(const sc_inout<bool> &port, bool val) argument 296 ::sc_gem5::newReset(&port, ::sc_gem5::Process::newest(), true, val); 300 sc_module::reset_signal_is(const sc_out<bool> &port, bool val) argument 302 ::sc_gem5::newReset(&port, ::sc_gem5::Process::newest(), true, val); 306 sc_module::reset_signal_is(const sc_signal_in_if<bool> &signal, bool val) argument 308 ::sc_gem5::newReset(&signal, ::sc_gem5::Process::newest(), true, val); 313 sc_module::async_reset_signal_is(const sc_in<bool> &port, bool val) argument 315 ::sc_gem5::newReset(&port, ::sc_gem5::Process::newest(), false, val); 319 async_reset_signal_is(const sc_inout<bool> &port, bool val) argument 325 async_reset_signal_is(const sc_out<bool> &port, bool val) argument 331 async_reset_signal_is(const sc_signal_in_if<bool> &signal, bool val) argument [all...] |
/gem5/src/arch/power/ |
H A D | process.cc | 241 auxv[i].val = platform_base; 244 auxv[i].val = aux_data_base; 284 PowerProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 287 tc->setIntReg(ArgumentReg0 + i, val);
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/gem5/src/arch/riscv/ |
H A D | process.cc | 243 DPRINTF(Stack, "Wrote aux value %x to address %#x\n", aux.val, sp); 244 pushOntoStack(aux.val); 267 RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 269 tc->setIntReg(SyscallArgumentRegs[i], val);
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/gem5/src/dev/x86/ |
H A D | cmos.hh | 54 void writeRegister(uint8_t reg, uint8_t val);
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/gem5/src/arch/x86/ |
H A D | utility.cc | 273 setRFlags(ThreadContext *tc, uint64_t val) argument 275 tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask); 276 tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask); 277 tc->setCCReg(X86ISA::CCREG_DF, val & DFBit); 285 tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));
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/gem5/src/arch/arm/kvm/ |
H A D | gic.cc | 290 auto val = from->readDistributor(ctx, daddr); local 291 DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val); 292 to->writeDistributor(ctx, daddr, val); 299 auto val = from->readCpu(ctx, daddr); local 300 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val); 301 to->writeCpu(ctx, daddr, val);
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/gem5/ext/systemc/src/sysc/datatypes/int/ |
H A D | sc_signed_subref.inc | 271 sc_digit val = 1; // Bit value. 278 m_obj_p->set(i + m_right, (bool) (d[j] & val)); 283 val = 1; 287 val <<= 1;
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H A D | sc_unsigned_subref.inc | 271 sc_digit val = 1; // Bit value. 278 m_obj_p->set(i + m_right, (bool) (d[j] & val)); 283 val = 1; 287 val <<= 1;
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/gem5/src/systemc/dt/int/ |
H A D | sc_signed_subref.inc | 274 sc_digit val = 1; // Bit value. 278 m_obj_p->set(i + m_right, (bool)(d[j] & val)); 281 val = 1; 284 val <<= 1;
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H A D | sc_unsigned_subref.inc | 268 sc_digit val = 1; // Bit value. 273 m_obj_p->set(i + m_right, (bool)(d[j] & val)); 276 val = 1; 279 val <<= 1;
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/gem5/src/systemc/tests/systemc/misc/stars/star110089/ |
H A D | star110089.cpp | 250 #define w_ctr(dev,val) (control = (val))
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/gem5/src/systemc/utils/ |
H A D | sc_report.cc | 114 sc_report::make_warnings_errors(bool val) argument 116 sc_gem5::reportWarningsAsErrors = val;
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/gem5/ext/testlib/ |
H A D | config.py | 184 val = self._lookup_val(attr) 185 if val is not None: 186 return val[0] 308 return (verbose[0].val,) 412 def __init__(self, val=0): 413 self.val = val 416 self.val += other
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